HT46R71D-1 Holtek Semiconductor, HT46R71D-1 Datasheet - Page 11

• Manufacturer Part Number: HT46R71D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

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interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becom-
ing full.
All interrupts will provide a wake-up function. As an in-
terrupt is serviced, a control transfer occurs by pushing
the contents of the program counter onto the stack fol-
lowed by a branch to a subroutine at the specified loca-
tion in the Program Memory. Only the contents of the
program counter is pushed onto the stack. If the con-
tents of the register or of the status register is altered by
the interrupt service program which corrupts the desired
control sequence, the contents should be saved in ad-
vance.
An external interrupt is triggered by an edge transition
on INT (A configuration option selects: high to low, low to
high, both low to high and high to low), and the related
interrupt request flag (EIF; bit 4 of INTC0) is set as well.
After the interrupt is enabled, the stack is not full, and
the external interrupt is active, a subroutine call to loca-
tion 04H occurs. The interrupt request flag (EIF) and
EMI bits are all cleared to disable other maskable inter-
rupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 5 of INTC0), which is normally
caused by a timer overflow. After the interrupt is en-
abled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 08H occurs. The related inter-
rupt request flag (T0F) is reset, and the EMI bit is
cleared to disable other maskable interrupts.
Timer/Event Counter 1 is operated in the same manner
but its related interrupt request flag is T1F (bit 6 of
INTC0) and its subroutine call location is 0CH.
The A/D Converter interrupt is initialized by setting the
A/D Converter clock interrupt request flag (ADF; bit 4 of
INTC1), that is caused by an A/D conversion done sig-
nal. After the interrupt is enabled, and the stack is not
full, and the ADF bit is set, a subroutine call to location
10H occurs. The related interrupt request flag (ADF) is
reset and the EMI bit is cleared to disable further
maskable interrupts.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the RETI instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1 (if the stack
is not full). To return from the interrupt subroutine, RET
or RETI may be invoked. RETI sets the EMI bit and en-
ables an interrupt service, but RET does not.
Rev. 1.00
11
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Once the interrupt request flags (ADF, T0F, T1F, EIF)
are all set, they remain in the INTC1 or INTC0 respec-
tively until the interrupts are serviced or cleared by a
software instruction.
It is recommended that a program should not use the
cause interrupts often occur in an unpredictable manner
or require to be serviced immediately in some applica-
tions. During that period, if only one stack is left, and en-
abling the interrupt is not well controlled, operation of
the call in the interrupt subroutine may damage the
original control sequence.
Oscillator Configuration
The device provides two oscillator circuits, an external
RC oscillator and an internal RC 12kHz oscillator
(Int.RCOSC). The external RC oscillator signal is used
for the system clock while the Internal 12kHz RC oscilla-
tor is designated for timing purposes.
In the IDLE mode, the system oscillator will stop run-
ning, but if bit IRCC = 1,to enable the IRC clock source,
the internal RC oscillator (Int.RCOSC) will continue to
free run. In the HALT mode, if the IRC clock source is
disabled, with bit IRCC=0, both the system oscillator
and the internal RC oscillator will stop running. How-
ever, if the WDT is enabled, the internal RC oscillator will
continuously free run. The system can be woken-up
from either the IDLE or HALT mode by the occurrence of
an interrupt, a high to low transition on any of the Port A
pins, a WDT overflow or a timer overflow and request
flag is set (0 1). If an external RC oscillator is used, an
CALL subroutine within the interrupt subroutine. It s be-
External interrupt
Timer/Event Counter 0 overflow
Timer/Event Counter 1 overflow
ADC interrupt
Interrupt Source
System Oscillator
HT46R71D-1
Priority
1
2
3
4
May 14, 2007
Vector
0CH
04H
08H
10H