HT46R71D-1 Holtek Semiconductor, HT46R71D-1 Datasheet - Page 15

• Manufacturer Part Number: HT46R71D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

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The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each pin
of port A can be independently selected to wake-up the
device using configuration options. After awakening
from an I/O port stimulus, the program will resume exe-
cution at the next instruction. However, if awakening
from an interrupt, two sequences may occur. If the re-
lated interrupt is disabled or the interrupt is enabled but
the stack is full, the program will resume execution at the
next instruction. But if the interrupt is enabled, and the
stack is not full, the regular interrupt response takes
place.
When an interrupt request flag is set before entering the
that interrupt.
If a wake-up events occur, it takes 1024 t
clock periods) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, the execution will be per-
formed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset may occur.
The WDT time-out during HALT or IDLE differs from
other chip reset conditions, for it can perform a warm
reset that resets only the program counter and SP and
leaves the other circuits at their original state. Some reg-
isters remain unaffected during any other reset condi-
tions. Most registers are reset to their initial conditions
once the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between
different chip resets.
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state or during power-up.
Awaking from the HALT state or system power-up, the
SST delay is added.
Rev. 1.00
HALT status, the system cannot be awakened using
TO PDF
RES is reset during normal operation
RES is reset during HALT
WDT time-out is reset during normal operation
0
u
0
1
1
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES Wake-up HALT
WDT time-out during normal operation
WDT Wake-up HALT
RESET Conditions
SYS
(system
15
An extra SST delay is added during the power-up pe-
riod, and any wake-up from HALT may enable only the
SST delay.
The functional unit chip reset status is shown below.
Note:
Program Counter
Interrupt
Prescaler, Divider
WDT
Timer/Event Counter
Input/output Ports
Stack Pointer
nected to the RES pin as short as possible, to
avoid noise interference.
* Make the length of the wiring, which is con-
Reset Configuration
Reset Timing Chart
Reset Circuit
000H
Disabled
Cleared
Cleared. After master reset,
WDT starts counting
Off
Input mode
Points to the top of the stack
HT46R71D-1
May 14, 2007