HT46R71D-1 Holtek Semiconductor, HT46R71D-1 Datasheet - Page 14

• Manufacturer Part Number: HT46R71D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

www.DataSheet4U.com
which is selected by configuration options to provide a
range of buzzer frequencies from f
clock source that generates f
buzzer frequency, can originate from two different
sources, the Int.RCOSC (Internal RC oscillator) or the
System oscillator/4, the choice of which is determined
by the f
buzzer frequency is controlled by configuration options,
which select both the source clock for the internal clock
f
registers associated with the buzzer frequency.
If the configuration options have selected both pins PA0
and PA1 to function as a BZ and BZ complementary pair
of buzzer outputs, then for correct buzzer operation it is
essential that both pins must be setup as outputs by set-
ting bits PAC0 and PAC1 of the PAC port control register
to zero. The PA0 data bit in the PA data register must
also be set high to enable the buzzer outputs, if set low,
both pins PA0 and PA1 will remain low. In this way the
single bit PA0 of the PA register can be used as an on/off
control for both the BZ and BZ buzzer pin outputs. Note
that the PA1 data bit in the PA register has no control
over the BZ buzzer pin PA1.
If configuration options have selected that only the PA0
pin is to function as a BZ buzzer pin, then the PA1 pin
can be used as a normal I/O pin. For the PA0 pin to func-
tion as a BZ buzzer pin, PA0 must be setup as an output
by setting bit PAC0 of the PAC port control register to
zero. The PA0 data bit in the PA data register must also
be set high to enable the buzzer output, if set low pin
PA0 will remain low. In this way the PA0 bit can be used
as an on/off control for the BZ buzzer pin PA0. If the
PAC0 bit of the PAC port control register is set high, then
pin PA0 can still be used as an input even though the
configuration option has configured it as a BZ buzzer
output.
Note that no matter what configuration option is chosen
for the buzzer, if the port control register has setup the
pin to function as an input, then this will override the con-
figuration option selection and force the pin to always
Rev. 1.00
S
and the internal division ratio. There are no internal
S
clock source configuration option. Note that the
S
, which in turn controls the
S
/2
2
to f
Buzzer Output Pin Control
S
/2
9
. The
14
behave as an input pin. This arrangement enables the
pin to be used as both a buzzer pin and as an input pin,
so regardless of the configuration option chosen; the ac-
tual function of the pin can be changed dynamically by
the application program by programming the appropri-
ate port control register bit.
Note:The above drawing shows the situation where
both pins PA0 and PA1 are selected by configuration op-
tion to be BZ and BZ buzzer pin outputs. The Port Con-
trol Register of both pins must have already been setup
as outputs. The data setup on pin PA1 has no effect on
the buzzer outputs.
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following.
The system leaves the HALT or IDLE mode by means of
an external reset, an interrupt, an external falling edge
signal on port A, or a WDT overflow. An external reset
causes device initialisation, and the WDT overflow per-
forms a warm reset . After examining the TO and PDF
flags, the reason for chip reset can be determined. The
PDF flag is cleared by system power-up or by executing
the CLR WDT instruction, and is set by executing the
WDT time-out occurs, and causes a wake-up that only re-
sets the program counter and SP, and leaves the others
in their original state.
HALT instruction. On the other hand, the TO flag is set if
The system oscillator turns off but the Internal oscilla-
tor (Int.RCOSC) keeps running (if the Internal oscilla-
tor is selected).
The contents of the on-chip RAM and of the registers
remain unchanged.
The WDT is cleared and starts recounting (if the WDT
clock source is from the Internal RC oscillator).
All I/O ports maintain their original status.
The PDF flag is set but the TO flag is cleared.
The LCD driver keeps running if the IRC clock is en-
abled; IRCC=0 and LCD on HALT mode set to ON.
HT46R71D-1
May 14, 2007