HT46R71D-1 Holtek Semiconductor, HT46R71D-1 Datasheet - Page 13

• Manufacturer Part Number: HT46R71D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

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When the WDTOSC is enabled, the Power Down mode
situation will be defined by the IRCC registers.
Once the internal RC oscillator, which has a nominal pe-
riod of 65 s, is selected, it is then divided by a value
which ranges from 2
determined by a configuration option, to obtain the ac-
tual WDT time-out period. The minimum period of the
WDT time-out period is about 300ms~600ms. This
time-out period may vary with temperature, VDD and
process variations. By using the related WDT configura-
tion option, longer time-out periods can be realized. If
the WDT time-out is selected to be 2
time-out period is divided by 2
time-out period of about 2.3s~4.7s.
The WDT clock source may also come from the instruc-
tion clock, in which case the WDT will operate in the
same manner except that in the Power Down mode the
WDT may stop counting and lose its protecting purpose.
In this situation the device can only be restarted by ex-
ternal logic. If the device operates in a noisy environ-
ment, using the on-chip RC oscillator (Int.RC OSC) is
strongly recommended, since the HALT instruction will
stop the system clock.
The WDT overflow under normal operation initializes a
IDLE mode, the overflow initializes a warm reset , and
only the PC and SP are reset to zero. There are three
methods to clear the contents of the WDT, an external
reset (a low level on RES), a software instruction or a
Note:
Rev. 1.00
chip reset and sets the status bit TO . In the HALT or
HALT instruction. There are two types of software in-
PAC Register
X stands for don t care
PAC.0
0
0
0
0
1
1
12
~2
15
PAC Register
the exact value of which is
PAC.1
15
~2
0
0
1
1
0
1
16
15
which will give a
, the maximum
PA0/PA1 Pin Function Control
PA data Register
Watchdog Timer
PA.0
0
1
0
1
0
X
13
structions; the single CLR WDT instruction, or the pair
of instructions
Of these two types of instruction, only one type of in-
struction can be active at a time depending on the con-
figuration option
If the CLR WDT is selected (i.e., CLR WDT times
equal one), any execution of the CLR WDT instruction
clears the WDT. If the CLR WDT1 and CLR WDT2
option is chosen (i.e., CLR WDT times equal two), these
two instructions have to be executed to clear the WDT,
otherwise the WDT may reset the chip due to a time-out.
Buzzer Output
The Buzzer function provides a means of producing a
variable frequency output, suitable for applications such
as Piezo-buzzer driving or other external circuits that re-
quire a precise frequency generator. The BZ and BZ
pins form a complimentary pair, and are pin-shared with
I/O pins, PA0 and PA1. A configuration option is used to
select from one of three buzzer options. The first option
is for both pins PA0 and PA1 to be used as normal I/Os,
the second option is for both pins to be configured as BZ
and BZ buzzer pins, the third option selects only the PA0
pin to be used as a BZ buzzer pin with the PA1 pin re-
taining its normal I/O pin function. Note that the BZ pin is
the inverse of the BZ pin which together generate a dif-
ferential output which can supply more power to con-
nected interfaces such as buzzers.
The buzzer is driven by the internal clock source, f
which then passes through a divider, the division ratio of
PA data Register
PA.1
X
X
X
X
X
X
CLR WDT1 and CLR WDT2 .
CLR WDT times selection option.
PA0=0, PA1=0
PA0=BZ, PA1=BZ
PA0=0, PA1=Input
PA0=BZ, PA1=Input
PA0=Input, PA1=0
PA0=Input, PA1=Input
Output Function
HT46R71D-1
May 14, 2007
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