HT46R71D-1 Holtek Semiconductor, HT46R71D-1 Datasheet - Page 19

• Manufacturer Part Number: HT46R71D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

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begins counting not according to the logic level but to
the transient edges. In the case of counter overflows,
the counter is reloaded from the timer/event counter
register and issues an interrupt request, as in the other
two modes, i.e., event and timer modes.
To enable the counting operation, the Timer ON bit
(T0ON; bit 4 of TMR0C or T1ON bit 4 of TMR1C) should
be set to 1. In the pulse width measurement mode, the
T0ON (T1ON) is automatically cleared after the mea-
surement cycle is completed. But in the other two
modes, the T0ON (T1ON) can only be reset by instruc-
tions. The overflow of the Timer/Event Counter 0/1 is
one of the wake-up sources. No matter what the opera-
tion mode is, writing a 0 to ET0I or ET1I disables the re-
lated interrupt service.
In the case of a timer/event counter OFF condition, writ-
ing data to the timer/event counter preload register also
reloads that data to the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter still contin-
ues its operation until an overflow occurs.
When the timer/event counter (reading TMR0/TMR1) is
read, the clock is blocked to avoid errors, however as
this may result in a counting error, it should be taken into
account by the programmer. It is strongly recommended
to load a desired value into the TMR0/TMR1 register
first, before turning on the related timer/event counter,
for proper operation since the initial value of
TMR0/TMR1 is unknown. Due to the timer/ event coun-
ter scheme, the programmer should pay special atten-
tion to the instructions which enables then disables the
timer for the first time, whenever there is a need to use
the timer/event counter function, to avoid unpredictable
results. After this procedure, the timer/event function
can be operated normally.
The bit0~bit2 of the TMR1C can be used to define the
pre-scaling stages of the internal clock sources of
Timer/Event Counter 1.
Input/Output Ports
There are 10 bidirectional input/output lines in the
microcontroller, labeled as PA and PB, which are
mapped to the data memory of [12H] and [14H] respec-
tively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction MOV A,[m] (m=12H or 14H).
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC) to
control the input/output configuration. With this control
register, CMOS outputs or Schmitt trigger inputs with or
without pull-high resistor structures can be reconfigured
dynamically under software control. To function as an in-
Rev. 1.00
19
put, the corresponding latch of the control register must
write 1 . The input source also depends on the control
register. If the control register bit is 1 , the input will
read the pad state. If the control register bit is 0 , the
contents of the latches will move to the internal bus. The
latter is possible in the read-modify-write instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
and 15H.
After a chip reset, these input/output lines remain at high
levels or in a floating state, depending upon the pull-high
configuration options. Each bit of these input/output
latches can be set or cleared by SET [m].i and CLR
[m].i (m=12H or 14H) instructions.
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor
connected. Take note that a non-pull-high I/O port setup
as an input mode will be in a floating condition.
Pins PA0, PA1, PA4, PA5 and PA6 are pin-shared with
BZ, BZ, TMR0, TMR1 and INT pins respectively.
PA0 and PA1 are pin-shared with BZ and BZ signal, re-
spectively. If the BZ/BZ configuration option is selected,
the output signals in the output mode of PA0/PA1 can be
the buzzer signal. The input mode always retains its
original function. Once the BZ/BZ configuration option is
selected, the buzzer output signals are controlled by the
PA0 data register.
The PA0/PA1 I/O function is shown below.
Note:
PA0 I/O
PA1 I/O
PA0 Mode
PA1 Mode
PA0 Data
PA1 Data
PA0 Pad Status
PA1 Pad Status
I input; O output
D, D0, D1 Data
B buzzer option, BZ or BZ
X don t care
C CMOS output
X X C B B C B B B B
X C X X X C C C B B
X X D 0
X D X X X D1 D D X X
I
I
I
I
O
D
I
I
O O O O O O O O
D 0 B D
I
I
I
I
1 D
I
I D
HT46R71D-1
O O O O O
0
0
1
D D 0 B
0
0 B 0 B
May 14, 2007
1
0
1