HT46R71D-1 Holtek Semiconductor, HT46R71D-1 Datasheet - Page 7

• Manufacturer Part Number: HT46R71D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

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Functional Description
Execution Flow
The system clock is derived from an RC oscillator. It is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each in-
struction to be effectively executed in a cycle. If an in-
struction changes the value of the program counter, two
cycles are required to complete the instruction.
Program Counter - PC
The program counter (PC) is 11 bits wide and it controls
the sequence in which the instructions stored in the pro-
gram ROM are executed. The contents of the PC can
specify a maximum of 2048 addresses.
After accessing a program memory word to fetch an in-
struction code, the value of the PC is incremented by 1.
Note:
Rev. 1.00
Initial Reset
External Interrupt
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
ADC Interrupt
Skip
Loading PCL
Jump, Call Branch
Return From Subroutine
*10~*0: Program counter bits
#10~#0: Instruction code bits
Mode
S10
#10
*10
*10
0
0
0
0
0
S9
#9
*9
*9
0
0
0
0
0
Program Counter
Execution Flow
#8
S8
*8
*8
0
0
0
0
0
7
@7
#7
S7
*7
0
0
0
0
0
The PC then points to the memory word containing the
next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading a PCL register, a subroutine call, an ini-
tial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; oth-
erwise proceed to the next instruction.
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL per-
forms a short jump. The destination is within 256 loca-
tions.
When a control transfer takes place, an additional
dummy cycle is required.
S10~S0: Stack register bits
@7~@0: PCL bits
Program Counter+2
Program Counter
@6
#6
S6
*6
0
0
0
0
0
@5
S5
#5
*5
0
0
0
0
0
@4
S4
#4
*4
0
0
0
0
1
@3
S3
#3
*3
0
0
1
1
0
@2
HT46R71D-1
S2
#2
*2
0
1
0
1
0
May 14, 2007
@1
S1
#1
*1
0
0
0
0
0
@0
S0
#0
*0
0
0
0
0
0