DS26502 Maxim Integrated Products, DS26502 Datasheet - Page 35

• Manufacturer Part Number: DS26502
• Description: T1/E1/J1/64KCC BITS Element
• Manufacturer: Maxim Integrated Products

Note 1:
Note 2:
Bits 4 to 7: Transmit Mode Configuration (TMODE[3:0]). Used to select the operating mode of the transmit path for the
DS26502.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
For more information on all the bits in the Transmit PLL control register, refer to
Bits 0 and 1: Transmit Clock (TX CLOCK) Source Select (TCSS[1:0]). These bits control the output of the TX PLL
Clock Mux function. See
Bit 2: Transmit PLL_CLK Source Select (TPLLSS). Selects the reference signal for the TX PLL.
TMODE3
TCSS1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
The DS26502 does not have an internal source for CAS signaling and multiframe alignment generation. CAS signaling, and the
In addition to setting the TMODE bits to 6312kHz Synchronization Interface mode, the Transmit PLL must also be configured to
0 = Use the recovered network clock. This is the same clock available at the RCLK pin (output).
1 = Use the externally provided clock present at the TCLK pin.
multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present on the TSER pin and frame
aligned to sync signal on the TS_8K_4 pin.
transmit a 6312kHz signal through the Transmit PLL Control Register (TPCR.6 and TPCR.7)
TPLLOFS1
TMODE2
TCSS0
7
0
0
0
1
0
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
Figure
TPLLOFS0
The TCLK pin is the source of transmit clock.
The PLL_CLK is the source of transmit clock.
The scaled signal present at MCLK as the transmit clock.
The signal present at RCLK is the transmit clock.
TPCR
Transmit PLL Control Register
09h
TMODE1
6
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
1
0
0
3-3.
TMODE0
PLLOS
5
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
Transmit Clock (TX CLOCK) Source
TPLLIFS0
T1 ESF (Note: In this mode the TFSE (T1TCR2.6) bit should be
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4
0
0
(See
Figure
64kHz + 8kHz + 400Hz Synchronization Interface
E1 G.703 2048 kHz Synchronization Interface
TPLLIFS1
6312kHz Synchronization Interface (Note 2)
64kHz + 8kHz Synchronization Interface
3-3)
3
0
0
Transmit Path Operating Mode
E1 CRC4 + CAS (Note 1)
E1 FAS + CAS (Note 1)
DS26502 T1/E1/J1/64KCC BITS Element
Figure
TPLLSS
E1 CRC4
Reserved
Reserved
Reserved
Reserved
set = 0.)
2
0
0
E1 FAS
J1 ESF
T1 D4
J1 D4
3-3.
TCSS1
TCSS1
PIN 31
1
0
TCSS0
TCSS0
PIN 63
0
0