DS26502 Maxim Integrated Products, DS26502 Datasheet - Page 95

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DS26502

Manufacturer Part Number
DS26502
Description
T1/E1/J1/64KCC BITS Element
Manufacturer
Maxim Integrated Products
Datasheet

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15. 64kHz SYNCHRONIZATION INTERFACE
The 64kHz synchronization interface conforms to G.703 requirements for Centralized Timing (option A),
Contradirectional Timing, and 64kHz Appendix II. It consists of a composite clock, where a 64kHz clock
signal is generated or decoded, along with embedded frequencies of 8kHz and 400Hz. Those signals
consist of AMI code with an 8kHz bipolar violation removed at every 400Hz. There are two separate
modes referred to in the specification, one with both the 64kHz clock and the 8kHz clock, and the second
with the 64kHz clock, the 8kHz clock, and the 400Hz clock.
Figure 15-1. 64kHz Composite Clock Mode Signal Format
15.1 Receive 64kHz Synchronization Interface Operation
In the receive path, the three clock frequencies are decoded from the AMI waveform with bipolar
violations that is received at the LIU interface. The 8kHz frequency and the 400Hz frequency are decoded
from the presence or absence of bipolar violations as described in G.703.
Table 15-1. Specification of 64kHz Clock Signal at Input Port
Frequency
Signal format
Alarm condition
400 Hz
8 kHz
Violation
125 us
a) 64kHz + 8kHz or
b) 64kHz + 8kHz + 400Hz
a) AMI with 8kHz bipolar violation,
b) AMI with 8kHz bipolar violation removed at every 400Hz
Alarm should not be occurred against the amplitude ranged
0.63-1.1 V
Violation
No
0-P
125 us
Violation
95 of 124
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Violation
125 us
DS26502 T1/E1/J1/64KCC BITS Element
Violation
125 us
Violation
No

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