DS26502 Maxim Integrated Products, DS26502 Datasheet - Page 43

• Manufacturer Part Number: DS26502
• Description: T1/E1/J1/64KCC BITS Element
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bits 0, 2, 5 to 7: Unused, must be set = 0 for proper operation.
Bit 1: Pulse-Density Enforcer Enable (PDE). The framer always examines the transmit and receive data streams for
violations of these, which are required by ANSI T1.403: No more than 15 consecutive zeros and at least N ones in each and
every time window of 8 x (N + 1) bits, where N = 1 through 23. When this bit is set to one, the DS26502 forces the transmitted
stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to
zero, as B8ZS encoded data streams cannot violate the pulse-density requirements.
Bit 3: Transmit AIS-CI Enable (TAIS-CI). Setting this bit causes the AIS-CI code to be transmitted from the framer to the
LIU, as defined in ANSI T1.403.
Bit 4: Transmit RAI-CI Enable (TRAI-CI). Setting this bit causes the ESF RAI-CI code to be transmitted in the FDL bit
position.
0 = disable transmit pulse-density enforcer
1 = enable transmit pulse-density enforcer
0 = do not transmit the AIS-CI code
1 = transmit the AIS-CI code
0 = do not transmit the ESF RAI-CI code
1 = transmit the ESF RAI-CI code
—
7
0
0
—
6
0
0
T1CCR
T1 Common Control Register
07h
—
5
0
0
TRAI-CI
4
0
0
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TAIS-CI
3
0
0
—
2
0
0
DS26502 T1/E1/J1/64KCC BITS Element
PDE
1
0
0
—
0
0
0