AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet
AN2244
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AN2244 Summary of contents
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... Freescale Semiconductor, Inc. Application Note AN2244/D Rev 1, 2/2002 Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface by Renaud Le Friec Within the telecommunications infrastructure, communication between devices is an essential and Scott Smith requirement. For example, banks of DSP resource are often used for applications such as voice ...
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MSC8101 Device Overview 1 MSC8101 Device Overview The 16-bit Motorola MSC8101 processor is the first member of the family of DSPs based on the StarCore™ SC140 core single device, this very versatile processor integrates the high-performance SC140 four-ALU ...
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Freescale Semiconductor, Inc. Also provided are the following: • The register settings for these modules as used by this application (Section 7, Source Code Files, Software Flow, and Register Settings). • The necessary hardware connections between the host MSC8101 device ...
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System Bus–HDI16 Host Interface Internally-Visible Registers HCR HSR HCVR HPCR HOTX HORX NOTE1: Both HOTX and HORX are FIFOs with a capacity of four 64-bit words HCR HSR HCVR ISR ICR CVR 16 16 Registers Visible to Host ...
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Freescale Semiconductor, Inc. The most important aspect of the HDI16 host interface for our purposes is that it is specified as an asynchronous interface, reducing concerns over clock skew between the HDI16 host interface and the host device buses. Furthermore, ...
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System Bus–HDI16 Host Interface Table 1. Physical MSC8101ADS Interconnects (Continued) Host MSC8101 Side System + CPM Edge Connector P1 P2 Pin No. Pin No. Signal Name D10 DREQ1 D8 DREQ2 D10 EXPGPL3 D12 EXPGPL5 B[1–3] C31, C32 0V C1, C3, ...
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Freescale Semiconductor, Inc. interrupt inputs consumed on the host processor but the disadvantage of using a single request for both directions. Therefore, either transmit and receive directions implement a known transfer protocol (for example, alternating Tx/Rx), or the host must ...
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HDI16 Device Configuration, Synchronization, and Set-Up MSC8101 Aggregator 2 SDRAM Channel 1 Source 32 Bytes 32 Bytes DMA FIFOs Channel 2 Destination 32 Bytes Destination 32 Bytes 32 Bytes FIFO empty (HTRQ) write request is issued. ...
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Freescale Semiconductor, Inc. MSC8101 software. Consequently, the HDI16 HDI16 side acts as a master during the synchronization process. When the HDI16-side software is ready to process commands sent from the host, it sets signal to the host that it is ...
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Host Device Configuration external memory or an internal peripheral and internal memory. The HDI16 MSC8101treats the HDI16 interface is an internal peripheral, making it easy to transfer data to and from the HDI16 interface and internal memory. 3.2.3 DMA Interrupts ...
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Freescale Semiconductor, Inc. To achieve these states, perform the following steps: 1. Configure the host memory controller to enable mapping of the HDI16 registers in memory. 2. Configure the host HDI16 registers, synchronize the host and HDI16 sides, and enable ...
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Host Device Configuration 4.3 Host I/O Ports The registers for the parallel I/O ports are configured, allowing the DMA controller via the DMA Request lines ( signals are enabled on Port C using the following registers: DREQ2 • Port Pin ...
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Freescale Semiconductor, Inc. • Transfer 1, Channel 1 — Attributes. Write Channel, NO_INC, Cyclic Address, Burst Transfer Size, Flush FIFO — Source Address. Host Transmit Word Registers of HDI16 — Size and Base Size. 32 bytes (one burst) • Transfer ...
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Hardware Timings Transfer Error Address Status Register (DTEAR) are cleared by writing a value of one (1) to all the bits, and the DMA Pin Configuration Register (DPCR) bits are cleared because we do not require it. 4.6 Host DMA ...
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Freescale Semiconductor, Inc. 0ns 250ns UPMClock BusClock 60x Addr Setup 60x Addr Setup 60x-Address HA[0:3] Setup HA[0:3]>DS Setup HA[0:3]>DS Setup HA[0:3] Setup HDS>HA[0:3] Hold HDI16-Ha[0:3] UPM-CS1 60x-CS1 CS1>HCS1 Delay HCS1>DS HDI16-HCS1 UPM-GPL5 UPM-GPL5 UPM-GPL5 60x-GPL5 GPL5>HDS Delay ...
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Physical MSC8101ADS Settings Table 2 defines the hexadecimal values loaded into the UPM RAM Array to obtain these timing signals. Cycle Type Single Read UPM Offset 0x0FFFFC00 offset + 0 0x0FFFF000 offset + 1 0x0FFFF000 offset + 2 0x0FFFF000 offset ...
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... Settings This application was developed using the Metrowerks 1.0. The CodeWarrior IDE provides a set of tools for developing software using a GUI. The Metrowerks project file references an 8101_Initialization.cfg file with which it can configure SDRAM and so on via the debugger. The location of this file can be modified to suit your own implementation of Metrowerks ...
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Source Code Files, Software Flow, and Register Settings Module Filename dma.c msc8101.h types.h Host MSC8101 Cont. hdi16.h hdi16masks.h dma.h dmatest.h Figure 8 and Figure 9 detail the software flow of both the HDI16 MSC8101 and host MSC8101 programs. Start Memory-Map ...
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Freescale Semiconductor, Inc. Start Store Tx test pattern in SDRAM Configure Memory Controller Bank 6 and Option Registers For Memory-Mapping HDI16 Host-Side Registers Load UPMA RAM Array Pattern Send Reset Configuration Word to HDI16 MSC8101 Host Flag 4 Set? No ...
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Source Code Files, Software Flow, and Register Settings Table 6 and Table 7 present the register settings for the HDI16 MSC8101 device and the host MSC8101 device. Unless indicated otherwise, all registers are described in detail in the MSC8101 Reference ...
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Freescale Semiconductor, Inc. Table 6. HDI16 MSC8101 Register Settings (Continued) Register DMA Channel 1 – DCHCR (0x80014105) “DMA Programming Model” in the chapter on DMA DMA Internal Mask Register (DIMR) (0 0x80000000 0x40000000) “DMA Programming Model” in the chapter on ...
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Source Code Files, Software Flow, and Register Settings Register DMA Channel 0 – BD_ATTR (0x40000230) “DMA Programming Model” in the chapter on DMA DMA Channel 0 – BD_BSIZE (0x20) “DMA Programming Model” in the chapter on DMA DMA Channel 0 ...
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Freescale Semiconductor, Inc. Table 7. Host MSC8101 Register Settings (Continued) Register DMA Channel 2 – BD_BSIZE (0x20) Section 15.6.1 of [1] DMA Channel 2 – DCHCR (0x40C20803 | 0xC0C20803) “DMA Programming Model” in the chapter on DMA DMA Channel 3 ...
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... Motorola, Inc. Metrowerks and CodeWarrior are registered trademarks of Metrowerks Corp. in the U.S. and/or other countries. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 AN2244/D For More Information On This Product, Go to: www.freescale.com ...