AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 2

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

MSC8101 Device Overview
1
2
1
For details on these MSC8101 modules, consult the following chapters of the MSC8101 Reference Manual: Chapter 14
(HDI16), Chapter 10 (memory controller), and Chapter 15 (DMA). For details on programming the HDI16 port and the
DMA controller, consult the MSC8101 User’s Guide.
MSC8101 Device Overview
The 16-bit Motorola MSC8101 processor is the first member of the family of DSPs based on the
StarCore™ SC140 core. On a single device, this very versatile processor integrates the high-performance
SC140 four-ALU (Arithmetic Logic Unit) DSP core with 512 KB of internal memory, a Communications
Processor Module (CPM), a 64-bit 60x-compatible bus, a very flexible system integration unit (SIU), and
a 16-channel DMA controller. With its four-ALU core, the MSC8101 can execute up to four
multiply-accumulate (MAC) operations in a single clock cycle. The MSC8101 CPM is a 32-bit
RISC-based communications protocol engine that can network to Time-Division Multiplexed (TDM)
highways, Ethernet, and Asynchronous Transfer mode (ATM) backbones. The very large internal
memory, 512 KB, reduces the need for external program and data memories. The MSC8101 offers 1200
DSP MIPS or 3000 RISC MIPS performance using an internal 300 MHz clock with a 1.6 V core and
independent 3.3 V input/output (I/O). MSC8101 power dissipation is estimated at 0.5 W.
Three key modules of the MSC8101 device that are crucial to the application discussed in this document
are as follows:
• Host interface (HDI16). A 16-bit wide, full-duplex, double-buffered parallel port that can connect
• Memory controller. Supports a glueless interface to the external memory and peripheral devices on the
• Multi-channel DMA Controller. Supports up to 16 time-division multiplexed channels and buffer
The host MSC8101 device must configure its memory controller to map the HDI16 host-side registers
into memory locations within its 60x system bus memory space. The HDI16 MSC8101 device configures
the HDI16 directly, treating it as an internal peripheral. After initial set-up of the HDI16 host interface,
the communication between the host MSC8101 device and the HDI16 MSC8101 device occurs via DMA
transfers, which are automatically triggered by signals generated from the HDI16 host interface. This
application note describes how to configure and use the HDI16 host interface, the memory controller, and
the DMA Controller.
directly to the data bus of a host processor. The HDI16 supports a variety of buses and gluelessly
connects to a number of industry-standard microcomputers, microprocessors, and DSPs. The HDI16
also supports the 8-bit host data bus, which makes it fully compatible with the DSP56300 HDI08 (as
viewed by the host side, not from the DSP side). The host bus can operate asynchronously to the SC140
core clock, and the HDI16 registers are divided into two banks. The host register bank is accessible to
the external host, and the core register bank is accessible to the SC140 core.
external system bus. It also enables interfacing with the internal DSP memory and DSP peripherals
residing on the internal local bus. Located on the external system bus, the memory controller controls a
maximum of eight memory banks shared by a high-performance SDRAM machine, a general-purpose
chip-select machine (GPCM), and two user-programmable machines (UPMs). It supports a glueless
interface to synchronous DRAM (SDRAM), SRAM, EPROM, flash EPROM, burstable RAM, regular
DRAM devices, extended data output DRAM devices, and other peripherals. Two additional memory
banks control access to resources using the local bus.
alignment by hardware. The DMA controller connects to both the system bus and the local bus and can
function as a bridge between both buses. The DMA controller enables hot swap between channels
using time-division multiplexed channels that impose no cost in clock cycles. Sixteen priority levels
support synchronous and asynchronous transfers on the bus and give a varying bus bandwidth per
channel.
Freescale Semiconductor, Inc.
For More Information On This Product,
1
Go to: www.freescale.com