AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 7

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

3
HDI16 Device Configuration, Synchronization, and
Set-Up
interrupt inputs consumed on the host processor but the disadvantage of using a single request for both
directions. Therefore, either transmit and receive directions implement a known transfer protocol (for
example, alternating Tx/Rx), or the host must poll the Interface Status Register (ISR) on each request to
determine the direction of data flow.
For ease of use and efficiency, we use Double Request mode. However, the request signals are not limited
to generating interrupts on the host device. They can also control DMA transfers across the interface,
which is useful because the SC140 core is not involved in a DMA transfer after initial set-up. The DMA
transfers can be configured to attempt to transfer n-bytes (the user-configured DMA transfer size) only
when the relevant external request signal (
more free locations within the HDI16 Rx FIFO, connecting it to a
DMA controller attempts to transfer data to the DSP only when there is a spare location. Similarly,
because the
connecting it to a
DSP only when data is present.
Note:
To facilitate burst transfers, the host’s 60x bus address lines are connected to dispose of certain 60x
signals:
• The host 60x
• We have also disposed of the 60x
Figure 3 shows how the host MSC8101 and HDI16 MSC8101 devices interact with each other through
their DMA channels. This section describes how to configure the HDI16 slave device to enable this
interaction. Section 4, Host Device Configuration, on page 10, describes how to configure the host
device. The HDI16 MSC8101 is configured to enable the HDI16 host interface for communications with
an external host MSC8101 as follows:
1. Configure the memory controller to map the HDI16 registers into memory.
2. Synchronize the HDI16 MSC8101 and host MSC8101 devices.
3. Set up and enable the DMA receive engine.
registers wrap around the same four 16-bit word addresses.
For example, the host can obtain the Host Transmit Register 0 on the HDI16 peripheral (address 0x04)
by accessing any of the following memory-mapped addresses: 0x20, 0x28, 0x30, or 0x38. This is
critical for burst accesses because the source or destination addresses increment after each 16-bit
access to the interface for all 16 transactions within that burst. Using the addressing as defined, if the
first access is at address 0x20, the last is at address 0x3E but, more importantly, the four host Tx/Rx
registers will have been looped around four times.
Until RevA of the MSC8101 device is available, the
status of 8-byte locations within the HDI16 FIFOs. Therefore, for real-world applications, the
DMA transfer size should be set at 8 bytes. However, to show how burst accesses across the
interface can be implemented, and because we know the number of bytes being transferred, this
application uses the
Freescale Semiconductor, Inc.
HRRQ
For More Information On This Product,
A31
DREQ
signal indicates one or more populated locations within the HDI16 Tx FIFO,
signal is not required because the HDI16 registers are 16-bit word addressed.
Go to: www.freescale.com
signal guarantees that the host DMA controller attempts to transfer data from the
HTRQ
and
A27
HDI16 Device Configuration, Synchronization, and Set-Up
HRRQ
and
DREQx
A28
signals to control burst transfers.
) is present. Because the
signals so that the host-side transmit and receive
HTRQ
DREQ
and
signal guarantees that the host’s
HRRQ
HTRQ
signals only indicate the
signal indicates one or
7