AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 23

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

DMA Channel 2 – BD_BSIZE
(0x20)
Section 15.6.1 of [1]
DMA Channel 2 – DCHCR
(0x40C20803 | 0xC0C20803)
“DMA Programming Model” in the chapter on DMA
DMA Channel 3 – BD_ADDR
(0x20000000 + Buffer Size)
“DMA Programming Model” in the chapter on DMA
DMA Channel 3 – BD_SIZE
(0x20)
“DMA Programming Model” in the chapter on DMA
DMA Channel 3 – BD_ATTR
(0x40000220)
“DMA Programming Model” in the chapter on DMA
DMA Channel 3 – BD_BSIZE
(0x20)
“DMA Programming Model” in the chapter on DMA
DMA Channel 3 – DCHCR
(0x40030044 | 0xC0030044)
“DMA Programming Model” in the chapter on DMA
DMA Internal Mask Register (DIMR)
(0)
“DMA Programming Model” in the chapter on DMA
Register
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 7. Host MSC8101 Register Settings (Continued)
Go to: www.freescale.com
0
1
8
9
10-15
17
19-23
25
28-31
0
1
2
4
22–24
26
27
0
1
10–15
17
25
28–31
Source Code Files, Software Flow, and Register Settings
Bits
0 | 1
1
1
1
000010
0
01000
0
0011
0
1
0
0
100
1
0
0 | 1
1
000011
0
1
0100
Setting
Size of the Rx buffer
Channel enabled or disabled
60x-compatible bus
DREQ level triggered
DREQ active low
Buffer Descriptor 2
Dual access transaction
External request DREQ 1
No internal requestor
Priority 3
Address of Rx buffer
Size of the Rx buffer
No interrupt
Cyclic address
No continuous buffer
Increment address
32-byte maximum transfer size
Flush FIFO
Write transaction
Size of the Rx buffer
Channel enabled or disabled
60x-compatible bus
Buffer Descriptor 3
Dual access transaction I
Internal requestor
Priority 4
Disable all DMA complete interrupts
Description
23