AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 13

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

4.5 Common Host Parameters
• Transfer 1, Channel 1
• Transfer 2, Channel 2
• Transfer 2, Channel 3
Channels 0 through 3 specify a cyclic address so that when a transfer completes, the pointer jumps back
to the base address, and the buffer is executed again. Channels 1 and 2 must also specify that they require
no incrementing of the address (NO_INC) to stop the automatic incrementing of the data address by eight
bytes once an eight-byte segment of the burst is transferred. The four 16-bit HDI16 Data Registers can
transfer only 8 bytes of a 32-byte burst at any one time, but after each 8-byte segment we still want to
point to the original address of these registers.
Since there are four DMA channels, four DMA Configuration Registers must be initialized. The content
of each register gives the following configurations for data transfers, all of which occur on the
60x-compatible system bus:
• Transfer 1, Channel 0: Internal Requestor. Buffer Descriptor 0 is used for this channel; the channel
• Transfer 1, Channel 1:
• Transfer 2, Channel 2:
• Transfer 2, Channel 3: Internal Requestor. Buffer Descriptor 3 is used for this channel; the channel
The DMA channels that transfer the data across the 60x:HDI16 interface (channel 1 for Tx and channel 2
for Rx) are controlled by
output via the HDI16 host interface. A transfer of n-bytes (where n is the DMA transfer size specified
within the buffer descriptor parameters for a specific channel) proceeds only when the relevant
signal is active.
Channels 0 and 3 use the Internal Requestor trigger to initiate a transfer. Each pair of DMA channels (0
and 1, 2 and 3, and so on) share a DMA FIFO, and the internal requestor triggers a DMA transfer
depending on the state of this FIFO. For example, here DMA Channel 0 is used to populate the DMA
FIFO by retrieving data from memory. Whenever there is enough free space within the FIFO to load
n-bytes (where n is the DMA transfer size), this DMA channel triggers. Similarly, DMA Channel 3
triggers whenever there is data within the FIFO that must be saved in memory.
— Attributes. Write Channel, NO_INC, Cyclic Address, Burst Transfer Size, Flush FIFO
— Source Address. Host Transmit Word Registers of HDI16
— Size and Base Size. 32 bytes (one burst)
— Attributes. Read Channel, NO_INC, Cyclic Address, Burst Transfer Size, Flush FIFO
— Source Address. Host Receive Word Registers of HDI16
— Size and Base Size. 32 bytes (one burst)
— Attributes. Write Channel, Cyclic Address, Burst Transfer Size, Flush FIFO
— Source Address. Received Test Pattern array within SDRAM
— Size and Base Size. 32 bytes (one burst)
priority level is 6.
Descriptor 1 is used for this channel; the channel priority level is 5.
Descriptor 2 is used for this channel; the channel priority level is 3.
priority level is 4.
Common host parameters are not needed in our application, so both internal and external DMA
interrupts are masked by clearing all bits in the DMA Internal Mask Register (DIMR) and DMA
External Mask Register (DEMR). For cleanliness, the DMA Status Register (DSTR) and the DMA
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DREQ
DREQ2
DREQ1
input signals. These signals connect to the
starts the transfer.
starts the transfer.
DREQ2
DREQ1
is level triggered and active low. Buffer
is level triggered and active low. Buffer
Host Device Configuration
HTRQ
and
HRRQ
signals
DREQ
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