AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 12

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

Host Device Configuration
4.3 Host I/O Ports
4.4 Host DMA Controller
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5
The I/O port registers are described in detail in the “Programming Model” section in the Parallel I/O Ports chapter of the
MSC8101 Reference Manual.
The format of these buffer descriptors is described in detail in the “Programming Model” section of the DMA chapter in
the MSC8101 Reference Manual.
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A transfer from SDRAM to the HDI16 is triggered by DREQ2 (Transfer 1).
A transfer from the HDI16 to SDRAM is triggered by DREQ1 (Transfer 2).
The host memory-maps the HDI16 host-side registers onto the 60x system bus.
SDRAM
The registers for the parallel I/O ports are configured, allowing the
DMA controller via the DMA Request lines (
DREQ2
• Port Pin Assignment Register C (PPARC): Bits PC24 and PC22 are set, and all other bits are cleared.
• Port Data Direction Register C (PDIRC): All bits are cleared.
• Port Special Option Register C (PSORC): Bits PC24 and PC22 set, and all other bits are cleared.
For cleanliness, the Port C Open-Drain Register (PODRC) and Port Data Register C (PDATC) are also
initialized, with all bits cleared.
This section describes how to enable the buffer descriptors and configure the DMA channels. The host
DMA controller must be configured to transfer data back and forth between the SDRAM and the HDI16.
The host MSC8101 treats the HDI16 as external memory on the 60x-compatible system bus, so we must
use Dual-Access mode instead of the DMA Flyby mode. We must configure two channels for each
complete DMA transfer. These transfers are triggered by the
Figure 5).
Because four DMA channels must be enabled to handle the two complete transfer mechanisms, four
buffer descriptors are configured as follows, one for each channel:
• Transfer 1, Channel 0
— Attributes. Read Channel, Cyclic Address, Burst Transfer Size, Flush FIFO
— Source Address. Transmit Test Pattern array within SDRAM
— Size and Base Size. 32 bytes (one burst)
DMA Channel 0
DMA Channel 3
signals are enabled on Port C using the following registers:
Figure 5. Host-Side DMA Channel Configuration
Freescale Semiconductor, Inc.
For More Information On This Product,
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(96 Bytes Deep)
(96 Bytes Deep)
DMA FIFO
DMA FIFO
DREQ1
DMA Channel 1
and
DMA Channel 2
DREQ2
DREQ1
, respectively). The
5
HRRQ
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and
DREQ2
and
60x Memory Map
HTRQ
request signals (see
signals to reach the
DREQ1
and
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