AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 15

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

HDI16-HD[0:15]
Direction Select
Direction Select
HDI16-Ha[0:3]
HDI16-Ha[0:3]
60x-Data[0:31]
60x-Data[0:31]
HDI16-HCS1
HDI16-HCS1
HDI16-HRW
HDI16-HRW
60x-Address
60x-Address
UPMClock
UPMClock
HDI16-DS
HDI16-DS
60x-GPL5
60x-GPL3
60x-GPL5
60x-GPL3
BusClock
BusClock
UPM-TA
UPM-TA
60x-CS1
60x-CS1
0ns
0ns
1
1
UPM-CS1
60x-GPL3 Setup
UPM-CS1
60x-GPL3 Setup
60x Addr Setup
60x Addr Setup
HA[0:3] Setup
HA[0:3] Setup
CS1>HCS1 Delay
GPL3>HRW Delay
Max7000 Direction
CS1>HCS1 Delay
GPL3>HRW Delay
Max7000 Direction
HCS1>DS
HCS1>DS
Direction Enable
60x Data
Direction Enable
60x Data
UPM-GPL5
UPM-GPL5
HA[0:3]>DS Setup
HA[0:3]>DS Setup
60x>HD[0:15] Data
Figure 7. Host MSC8101 60x-to-HDI16 MSC8101 Host Port Read Timing
GPL5>HDS Delay
Figure 6. Host MSC8101 60x-to-HDI16 MSC8101 Host Port Write Timing
GPL5>HDS Delay
2
2
HD[0:15] Setup
HDS Assert
HDS Assert
HD[0:15] Setup
HDS Assert
HDS Assert
UPM-GPL5
UPM-GPL5
GPL5>HDS Delay
GPL5>HDS Delay
HDS Deassert
HDS Deassert
HDS Deassert
HDS Deassert
HD[0:15] Hold
HD[0:15] Hold
TA Latch
TA Latch
TA>Data Invalid
TA>Data Invalid
TA>HD[0:15] HiZ
HDS>HA[0:3] Hold
HDS>HA[0:3] Hold
60x Addr Setup
60x Data
60x Addr Setup
60x Data
TA Deassert
TA Deassert
HA[0:3] Setup
60x>HD[0:15] Data
HA[0:3] Setup
60x>HD[0:15] Data
Freescale Semiconductor, Inc.
UPM-GPL5
UPM-GPL5
HA[0:3]>DS Setup
HA[0:3]>DS Setup
GPL5>HDS Delay
GPL5>HDS Delay
For More Information On This Product,
250ns
250ns
3
3
UPM-GPL5
HD[0:15] Setup
HDS Assert
HDS Assert
UPM-GPL5
HD[0:15] Setup
HDS Assert
HDS Assert
GPL5>HDS Delay
GPL5>HDS Delay
HDS Deassert
HDS Deassert
HDS Deassert
HDS Deassert
HD[0:15] Hold
HD[0:15] Hold
TA Latch
TA Latch
TA>Data Invalid
TA>Data Invalid
TA>HD[0:15] HiZ
HDS>HA[0:3] Hold
HDS>HA[0:3] Hold
60x Addr Setup
60x Data
60x Addr Setup
60x Data
TA Deassert
TA Deassert
Go to: www.freescale.com
HA[0:3] Setup
60x>HD[0:15] Data
HA[0:3] Setup
60x>HD[0:15] Data
UPM-GPL5
UPM-GPL5
HA[0:3]>DS Setup
HA[0:3]>DS Setup
GPL5>HDS Delay
GPL5>HDS Delay
4
4
HD[0:15] Setup
HDS Assert
HDS Assert
HD[0:15] Setup
HDS Assert
HDS Assert
UPM-GPL5
UPM-GPL5
GPL5>HDS Delay
GPL5>HDS Delay
HDS Deassert
HDS Deassert
HDS Deassert
HDS Deassert
HD[0:15] Hold
HD[0:15] Hold
TA Latch
TA Latch
TA>Data Invalid
TA>Data Invalid
TA>HD[0:15] HiZ
HDS>HA[0:3] Hold
HDS>HA[0:3] Hold
60x Addr Setup
TA Deassert
60x Data
60x Addr Setup
TA Deassert
60x Data
HA[0:3] Setup
60x>HD[0:15] Data
HA[0:3] Setup
60x>HD[0:15] Data
UPM-GPL5
UPM-GPL5
HA[0:3]>DS Setup
HA[0:3]>DS Setup
GPL5>HDS Delay
GPL5>HDS Delay
500ns
500ns
HD[0:15] Setup
HDS Assert
HDS Assert
HD[0:15] Setup
HDS Assert
HDS Assert
UPM-GPL5
UPM-GPL5
5
5
HDS>HA[0:3] Hold
HDS>HA[0:3] Hold
DS>HRW Hold
DS>HRW Hold
GPL5>HDS Delay
GPL5>HDS Delay
DS>HCS
DS>HCS
HD[0:15] Hold
HD[0:15] Hold
TA Data Latch
TA Data Latch
TA>Data Invalid
TA>Data Invalid
TA>HD[0:15] HiZ
UPM-CS1
UPM-CS1
TA Deassert
TA Deassert
60x-GPL3 Setup
60x-GPL3 Setup
CS1>HCS1 Delay
CS1>HCS1 Delay
60x Addr Setup
60x Addr Setup
GPL3>HRW Delay
Max7000 Direction
GPL3>HRW Delay
Max7000 Direction
6
6
750ns
750ns
UPM-CS1
60x-GPL3 Setup
UPM-CS1
60x-GPL3 Setup
60x Addr Setup
60x Addr Setup
HA[0:3] Setup
HA[0:3] Setup
CS1>HCS1 Delay
GPL3>HRW Delay
Max7000 Direction
CS1>HCS1 Delay
GPL3>HRW Delay
Max7000 Direction
Direction Enable
60x Data
Direction Enable
60x Data
HCS1>DS
HCS1>DS
60x>HD[0:15] Data
HA[0:3]>DS Setup
HA[0:3]>DS Setup
UPM-GPL5
UPM-GPL5
7
7
GPL5>HDS Latency
GPL5>HDS Latency
Hardware Timings
HD[0:15] Setup
HDS Assert
HDS Assert
HD[0:15] Setup
HDS Assert
HDS Assert
UPM-GPL5
UPM-GPL5
GPL5>HDS Delay
GPL5>HDS Delay
8
8
HD[0:15] Hold
HD[0:15] Hold
TA Data Latch
TA>Data Invalid
TA Data Latch
TA>Data Invalid
TA>HD[0:15) HiZ
HDS>HA[0:3] Hold
HDS>HA[0:3] Hold
60x Addr Setup
TA Deassert
60x Data
60x Addr Setup
TA Deassert
60x Data
HA[0:3] Setup
60x>HD[0:15] Data
HA[0:3] Setup
60x>HD[0:15] Data
15