AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 21

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

DMA Channel 1 – DCHCR (0x80014105)
“DMA Programming Model” in the chapter on DMA
DMA Internal Mask Register (DIMR) (0
0x80000000 0x40000000)
“DMA Programming Model” in the chapter on DMA
Memory Controller Option Register 6 (OR6)
(0XFFF00000)
“Memory Controller Programming Model” in the
chapter on the Memory Controller
Memory Controller Base Register 6 (BR6)
(0x30001081)
“Memory Controller Programming Model” in the
chapter on the Memory Controller
Machine A Mode Register (MAMR)
(0 | 0x10000000)
“Memory Controller Programming Model” in the
chapter on the Memory Controller
HDI16 Interface Control Register (ICR)
(0x0607)
“External Host-Side Programming Model” in the
chapter on the Host Interface (HDI16)
Port C – Port Pin Assignment Register (PPARC)
(0x00000280)
“Parallel I/O Ports Programming Model” in the
chapter on Parallel I/O Ports
Port C – Port Special Option Register (PSORC)
(0x00000280)
“Parallel I/O Ports Programming Model” in the
chapter on Parallel I/O Ports
Port C – Port Data Direction Register (PDIRC)
(0x00000000)
“Parallel I/O Ports Programming Model” in the
chapter on Parallel I/O Ports
DMA Channel 0 – BD_ADDR
(0x20000000)
“DMA Programming Model” in the chapter on DMA
DMA Channel 0 – BD_SIZE
(0x20)
“DMA Programming Model” in the chapter on DMA
Register
Register
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 6.
Table 7. Host MSC8101 Register Settings
Go to: www.freescale.com
HDI16 MSC8101 Register Settings (Continued)
0
1
10–15
17
19–23
28–31
0
1
0–16
23
0–16
19–20
24–26
31
5
6
13
14
15
22
24
22
24
22
24
2–3
Source Code Files, Software Flow, and Register Settings
Bits
Bits
11111111
11110000
0
0
00110000
00000000
0
10
100
1
00 | 01
0 | 1
0 | 1
1
1
1
1
1
1
1
0
0
1
0
000001
1
00001
0101
0 | 1
0 | 1
Setting
Setting
Channel is enabled
Local bus
Buffer Descriptor 1
Flyby mode
HDI16 write request
Priority 5
Enable or disable channel 0 interrupts
Enable or disable channel 1 interrupts
The corresponding address bits are used
in the comparison with address pins. The
banks support bursts.
Bank address
16-bit port size
UPM A machine select
Valid bank
Normal operation | Write to array
Host Flag 0 on or off
Host Flag 1 on or off
Select HTRQ and HRRQ signals
Enable HTRQ generation
Enable HRRQ generation
DMA DREQ 1
DMA DREQ 2
DMA DREQ 1
DMA DREQ 2
Input
Input
Address of Tx buffer
Size of the Tx buffer
Description
Description
21