AN2442 Freescale Semiconductor / Motorola, AN2442 Datasheet

AN2442

Manufacturer Part Number

AN2442

Description

Booting the MSC8102 Device Through TDM

Manufacturer

Freescale Semiconductor / Motorola

Datasheet

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Application Note

AN2442/D

Rev. 0, 1/2003

Booting the MSC8102

Device Through TDM

by Barbara Johnson

CONTENTS

1 Detecting Boot Mode..... 1

2 Synchronizing the Boot

3 Initializing the TDM ...... 3

4 Perform the Block

4.1 Block Transfer

4.2 Block Transfer

5 Example Boot Master

5.1 Initialize the Boot

5.2 Initialize the TDM

5.3 Initialize the

5.4 Configure the Buffer

5.5 Initialize the MCC

5.6 Configure the Serial

5.7 Enable the TDM ........ 18

Signals ........................... 1

Transfer of Code

and Data ........................ 5

Code............................. 10

Message....................... 5

Acknowledge Message 8

Mode.......................... 10

Pins ........................... 11

Transmit and Receive

Buffers ....................... 13

Descriptors................ 14

Parameters ................ 15

Interface .................... 17

The Motorola StarCore

interface in which a boot master downloads program and data to one or more MSC8102 devices. This

application note discusses the steps in the bootloader program:

• detect the selected boot mode

• synchronize to the boot master TDM signals

• initialize the TDM

• begin the block transfer protocol.

This document also provides example boot master code that uses the MSC8101 to boot the MSC8102

from the TDM module.

The MSC8102 operating mode is configured by the external boot mode

on the rising edge of

are copied to the BM field in the SIU Module Configuration Register (SIUMCR). The bootloader

program checks this field to determine the boot mode. If SIUMCR[7–9]:BM = 010, the MSC8102 device

is configured to boot through the TDM interface. The bootloader program jumps to the TDM boot section

in the ROM.

An MSC8102 TDM boot system consists of a boot master and one or more slave MSC8102 devices. The

boot master generates the clock and frame sync signals for both the receive and transmit. The MSC8102

device must determine the frame parameters so that it can initialize the number of channels and the size

of each channel in the TDM. The MSC8102 TDM adaptation machine synchronizes with the boot master

frame sync signal to determine these frame parameters. Figure 1 shows an example TDM boot system.

The bootloader program enables the TDM adaptation machine and waits for a receive frame sync to

arrive. It checks the number of bits between the last back-to-back receive frame sync events. This check

is repeated until the number of bits is stable 16 times. The same frame sync detection and procedure

occurs for the transmit frame sync. The adaptation machine is disabled after the frames are determined to

be stable. Figure 2 shows the flow diagram of the synchronization procedure.

A TDM frame has an even number of channels, and the channel size can be an even number of bits up to

256 bits. For example:

• When there are 8 bits in a frame, each of the two channels is 4 bits wide.

• When there are 16 bits in a frame, each of the two channels is 8 bits wide.

Detecting Boot Mode

Synchronizing the Boot Signals

Freescale Semiconductor, Inc.

For More Information On This Product,

PORESET

Go to: www.freescale.com

MSC8102 device supports booting from the time-division multiplexing (TDM)

. As part of the reset configuration sequence, the logic states of these pins

BM[0–2]

pins, which are sampled

Related parts for AN2442

AN2442 Summary of contents

Page 1

... Freescale Semiconductor, Inc. Application Note AN2442/D Rev. 0, 1/2003 Booting the MSC8102 Device Through TDM by Barbara Johnson The Motorola StarCore interface in which a boot master downloads program and data to one or more MSC8102 devices. This application note discusses the steps in the bootloader program: CONTENTS • ...

Page 2

Synchronizing the Boot Signals • When there are 32 bits in a frame, each of the four channels is 8 bits wide . • When there are 193 bits in a frame, each of the 24 channels is 8 bits ...

Page 3

Freescale Semiconductor, Inc. The TDM3 Receive Frame Parameters Register (TDM3RFP) and the TDM3 Transmit Frame Parameters Register (TDM3TFP) are configured according to the detected frame size. The TDM3RFP[8–15]:RNCF and TDM3TFP[8–15]:TNCF are updated with the number of channels in the TDM ...

Page 4

Initializing the TDM The receive frame sync is active on logic ‘1.’ Both the receive frame sync and the receive data are sampled on the rising edge of the receive clock. The receive frame sync occurs one cycle before the ...

Page 5

Freescale Semiconductor, Inc. 4 Perform the Block Transfer of Code and Data The boot master device writes blocks of code and data into the memory of one or more MSC8102 devices. The MSC8102 implements a block transfer protocol to ensure ...

Page 6

Perform the Block Transfer of Code and Data destination address of 0x01010000. Again, the least significant byte of the address is sent first. The next two bytes are the result of the CRC-16 calculation of the header fields, which is ...

Page 7

Freescale Semiconductor, Inc. org p:$020c0000 nop move.l emr,d1 move.l #$8000,r5 nop move.l d1,(r5) nop wait nop org p:$02100000 nop move.l emr,d1 move.l #$8000,r5 nop move.l d1,(r5) nop wait nop org p:$02140000 nop move.l emr,d1 move.l #$8000,r5 nop move.l d1,(r5) nop ...

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Perform the Block Transfer of Code and Data 4.2 Block Transfer Acknowledge Message The BTAM is the message that the slave MSC8102 sends back to the boot master. It contains information about the previously received BTM (see Table 3). Block ...

Page 9

Freescale Semiconductor, Inc. and SCID with my CHIP_ID End TDM Boot Session Figure 7. MSC8102 Logic Layer Protocol Figure 8 shows the BTAMs sent from the MSC8102 to the boot master device. The MSC8102 device with a CHIP_ID value of ...

Page 10

Example Boot Master Code The boot master device works in either the handshake mode or the non-handshake mode. The handshake mode implements a stop and wait technique in which the boot master waits for the BTAM message after sending the ...

Page 11

Freescale Semiconductor, Inc. ; ------------------------------------------- ; Initialize MSC8102 boot mode ; ; MSC8101 - 66 MHz oscillator ; MSC8102 - 41.6 MHz oscillator ; ; MSC8102ADS switch settings ; SW4[1:4] = OFF OFF ON OFF ; SW6[1: OFF ...

Page 12

Example Boot Master Code ; ------------------------------------------- ; Pin Configuration ; PC31 - CLK1 ; PC30 - CLK2 ; PC29 - TIN2 ; PC28 - TOUT2_B ; PC27 - BRG5O ; ------------------------------------------- ; Configure TDM pins write_l #$03c00000,PPARA write_l #$03c00000,PSORA write_l ...

Page 13

Freescale Semiconductor, Inc. 5.3 Initialize the Transmit and Receive Buffers The example discussed in this section uses one buffer for each channel so that there are four transmit buffers and four receive buffers. Each buffer holds 0x1000 bytes of data. ...

Page 14

Example Boot Master Code 5.4 Configure the Buffer Descriptors The buffer descriptors contain the control and status information for the buffers, buffer location, and buffer data length. The code to configure the buffer descriptors is shown in Example 5. This ...

Page 15

Freescale Semiconductor, Inc. 5.5 Initialize the MCC Parameters MCC initialization consists of several steps as described here. The initialization code is shown in Example 6. 1. Initialize the MCC parameters to their reset state. This step issues the INIT RX ...

Page 16

Example Boot Master Code nop bf _loop_cpcr ; ------------------------------------------- ; Set up MCC Global Parameters ; ------------------------------------------- write_l #MCCBASE_CNFG,MCC1_MCCBASE write_w #$0,MCC1_STATE write_w #MCC1_MRBLR_CNFG,MCC1_MRBLR write_w #$0,MCC1_GRFTHR write_w #$0,MCC1_GRFCNT write_l #$0,MCC1_RINTTMP write_l #$0,MCC1_DATA0 write_l #$0,MCC1_DATA1 write_l #TINTBASE_CNFG,MCC1_TINTBASE write_l #TINTBASE_CNFG,MCC1_TINTPTR write_l #$0,MCC1_TINTTMP write_w ...

Page 17

Freescale Semiconductor, Inc. bf _loop_extra_param ; ---------------------------------------------- ; Set up Channel-Specific Parameters Transparent ; ---------------------------------------------- move.l #DPRAM1,r0 move.l #RNUM_CH,d0 _loop_specific_param write_l #$1b800000,(r0)+ write_l #$10000207,(r0)+ write_l #$ffffffff,(r0)+ write_l #$ffffffff,(r0)+ write_w #$0000,(r0)+ write_w #$0000,(r0)+ write_l #$00000000,(r0)+ write_w #$0303,(r0)+ write_w #$7600,(r0)+ adda write_l ...

Page 18

Example Boot Master Code data on TDMA1 to MCC1 channels 0 through 3. Similarly, the transmit SI RAM is programmed to route four bytes data from MCC1 channels 0 through 3 on TDMA1. The SI1 configuration code is shown in ...

Page 19

Freescale Semiconductor, Inc. NOTES: For More Information On This Product, Go to: www.freescale.com Example Boot Master Code 19 ...

Page 20

... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark and StarCore is a registered trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 AN2442/D For More Information On This Product, Go to: www.freescale.com ...

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