AN2442 Freescale Semiconductor / Motorola, AN2442 Datasheet - Page 17

• Manufacturer Part Number: AN2442
• Description: Booting the MSC8102 Device Through TDM
• Manufacturer: Freescale Semiconductor / Motorola

5.6 Configure the Serial Interface
; ----------------------------------------------
; Set up Channel-Specific Parameters Transparent
; ----------------------------------------------
_loop_specific_param
; -------------------------------------------
; Set up MCC Control Registers
; -------------------------------------------
; Connect
; MCC1 enable RINT0 and TINT interrupts
; MCC2 is not active
; Clear the MCC event registers
Serial interface 1 (SI1) is programmed to connect to the TDMA1 channels. The SI1 Mode Register
(SI1AMR) programs the first bank of the SI RAM for TDMA1 and sets TDMA1 to operate in normal
mode. It also configures a 1-bit delay between the receive frame sync and the first bit of the receive
frame. The frame sync is active on logic ‘1’ and is sampled on the rising edge. Transmit data is driven out
on the falling edge, and receive data is sampled on the rising edge of the clock. These frame parameters
are set to meet the MSC8102 TDM frame parameter requirements.
The SI1 RAM entries define how the MCC1 data are routed on the TDMA. The transmit and receive SI1
RAM start at offsets of 0x12000 and 0x12400 from the dual-port memory, respectively. Since this
example uses four 8-bit channels per frame, the receive SI RAM is programmed to route four bytes of
bf _loop_extra_param
move.l #DPRAM1,r0
move.l #RNUM_CH,d0
write_l #$1b800000,(r0)+
write_l #$10000207,(r0)+
write_l #$ffffffff,(r0)+
write_l #$ffffffff,(r0)+
write_w #$0000,(r0)+
write_w #$0000,(r0)+
write_l #$00000000,(r0)+
write_w #$0303,(r0)+
write_w #$7600,(r0)+
adda
write_l #$1b800000,(r0)+
write_l #$50ffffe0,(r0)+
write_l #$ffffffff,(r0)+
write_l #$ffffffff,(r0)+
adda
write_w #MCC1_MRBLR_CNFG,(r0)+
write_w #$5555,(r0)+
adda
deceq d0
bf _loop_specific_param
write_b #$0,MCCF1
write_b #$0,MCCF2
write_w #$4004,MCCM1
write_w #$0000,MCCM2
write_w #$ffff,MCCE1
write_w #$ffff,MCCE2
Freescale Semiconductor, Inc.
For More Information On This Product,
to TDMA ports to MCC1
#$4,r0 ; Reserved
#$8,r0
#$4,r0
Go to: www.freescale.com
; TSTATE
; ZISTATE
; ZIDATA0
; ZIDATA1
; TxBD flag
; TBDCNT
; TBPTR
; INTMSK
; CHAMR
; RSTATE
; ZDSTATE
; ZDDATA0
; ZDDATA1
; Read-only
; MRBLR
; Next channel
Example Boot Master Code
17