AN2442 Freescale Semiconductor / Motorola, AN2442 Datasheet - Page 15

• Manufacturer Part Number: AN2442
• Description: Booting the MSC8102 Device Through TDM
• Manufacturer: Freescale Semiconductor / Motorola

5.5 Initialize the MCC Parameters
MCC initialization consists of several steps as described here. The initialization code is shown in
Example 6.
1. Initialize the MCC parameters to their reset state.
2. Initialize the MCC global parameters.
3. Initialize the MCC channel extra parameters.
4. Initialize the MCC channel-specific parameters.
5. Initialize the MCC control and event registers.
; -------------------------------------------
; Issue Init Parameters command
; -------------------------------------------
write_l #$1f810000,CPCR
_loop_cpcr
This step issues the INIT RX AND TX PARAMS command to the Communications Processor
Command Register (CPCR) to initialize the MCC1 parameters to their reset values. Since the
command initializes 32 consecutive channels, the command is issued only once to initialize the four
channels used in this example.
This step initializes the MCC1 parameters that are common to all channels.:
— The base address of the buffer descriptors MCCBASE_CNFG is set to location 0x02000000.
— The base address of the transmit interrupt queue TINTBASE_CNFG is set to location
— The base address of the receive interrupt queue RINTBASE0_CNFG is set to location
— The base address of the channel extra parameters XTRABASE_CNFG is set to 0x3800.
Each channel uses 8 bytes of extra parameters placed in the dual-port memory at offset
XTRABASE_CNFG + (8 × channel number). This step sets the channel receive and transmit buffer
descriptor tables relative to MCCBASE_CNFG. For example, the receive buffer descriptor base
address RBASE for channel 0 is located at MCCBASE_CNFG + 8 × 0 = 0x02000000. The receive
buffer descriptor base address RBASE for channel 1 is located at MCCBASE_CNFG + 8 × 1=
0x02000008. The base transmit buffer descriptor base address TBASE is calculated the same way.
Each channel uses 64 bytes of channel-specific parameters placed in the dual-port memory at offset
64 × channel number. This example assumes transparent operation, so the channel-specific
parameters for transparent channels are used.
— TSTATE and RSTATE provide transaction parameters associated with SDMA channel accesses
— The interrupt mask INTMSK parameter enables underrun, busy, transmit buffer, and receive
— The channel mode CHAMR parameter sets the channels to operate in transparent mode and
This step programs the MCC1 Configuration Register (MCCF1) to map the MCC1 channels to
TDMA1. It also enables receive and transmit interrupts.
move.l (CPCR),d0
nop
bmtstc #$0001,d0.h
0x02078000.
0x02070000. Interrupt queues 1 to 3 are not used. Also, this example does not use a superchannel
table.
and start the transmit and receive channel, respectively. This example selects the local bus SDMA
to handle transfers to and from the data buffers, buffer descriptors, and interrupt queues.
buffer events to be written to the interrupt queue when the events occur.
activates the channels.
Freescale Semiconductor, Inc.
For More Information On This Product,
Example 6. Initialize the MCC Parameters
Go to: www.freescale.com
Example Boot Master Code
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