AN2442 Freescale Semiconductor / Motorola, AN2442 Datasheet - Page 10

• Manufacturer Part Number: AN2442
• Description: Booting the MSC8102 Device Through TDM
• Manufacturer: Freescale Semiconductor / Motorola

Example Boot Master Code
5
5.1 Initialize the Boot Mode
10
Example Boot Master Code
The boot master device works in either the handshake mode or the non-handshake mode. The handshake
mode implements a stop and wait technique in which the boot master waits for the BTAM message after
sending the BTM. If the boot master does not receive a BTAM within a 32-frame time period, it resends
the BTM and waits for a BTAM again. This method should be used to ensure proper operation. In the
non-handshake mode, the boot master device does not wait for the BTAM messages. Instead, the BTM
messages are sent in sequence without any wait time. The MSC8102 device returns the BTAM messages,
but their correctness is not guaranteed.
This section illustrates how to boot the MSC8102 device from the TDM module using the
MSC8102ADS. The on-board MSC8101 is configured as the boot master, and the slave MSC8102 device
CHIP_ID is set to 3. The MSC8101 Multichannel Controller 1 (MCC1) performs the TDM
communication. The MSC8101 and MSC8102 are clocked with 66 MHz and 41.6 MHz oscillators,
respectively. Note that other devices with a TDM interface can be used as the boot master.
The boot mode selection and initialization proceeds as follows:
1. Assign the BTMD[0–2] field a value of 0b010 to boot from the TDM by writing a value of 0xFA to
2. Select the reset configuration mode and configuration source by writing a value of 0x07 to Board
3. Initiate the power-on-reset sequence by writing a value of 0x7F to the Board Control/Status Register
After the power-on-reset sequence, the MSC8102 executes the TDM bootloader program in ROM. The
boot master is now ready to send messages to the slave MSC8102 device. Example 1 shows how to
initialize the boot mode. The example code in this application note uses the macros write_l, write_w, and
write_b to move long word, word, and byte-sized data to a register.
Board Control/Status Register 3 (BCSR3).
The values written to BCSR3 BTMD[0–2] drive the boot mode
power-on-reset sequence.
Control/Status Register 2 (BCSR2).
This step clears the RSTCNF and CNFGS fields so that the Hard Reset Configuration Word (HRCW)
is written through the system bus. It also sets the MSC8102 as the configuration master. In this
example, the HRCW is programmed from the on-board Flash EPROM. The values written to
BCSR2[RSTCNF] and BCSR2[CNFGS] drive the
power-on-reset sequence.
1 (BCSR1).
This step clears the RECONF field to assert the
the
PORESET
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signal.
Figure 8. Acknowledge Messages
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5566030130E3
5566030270E2
55660303B122
55660304F0E0
556603053120
556603067121
55660307B0E1
PORESET
RSTCONF
signal. Writing 0xFF to BCSR1 negates
and
BM[0–2]
CNFGS
pins during the
pins during the