AN2442 Freescale Semiconductor / Motorola, AN2442 Datasheet - Page 4

• Manufacturer Part Number: AN2442
• Description: Booting the MSC8102 Device Through TDM
• Manufacturer: Freescale Semiconductor / Motorola

Initializing the TDM
4
TDMxTSYN
Channel number
TDMxTCLK
TDMxTDAT
Channel number
TDMxRCLK
TDM0RSYN
TDM0RDAT
Data sampled
The receive frame sync is active on logic ‘1.’ Both the receive frame sync and the receive data are
sampled on the rising edge of the receive clock. The receive frame sync occurs one cycle before the first
bit of the receive data is sampled. Figure 3 shows the relative timing of the receive section of the TDM.
The transmit frame sync is active on logic ‘1.’ The transmit frame sync is sampled on the rising edge of
the transmit clock. The transmit data is driven out on the falling edge of the clock. The transmit frame
sync occurs one-half cycle before the first bit of the transmit data is driven out. Figure 4 shows the
relative timing of the transmit section of the TDM.
The boot master transmits messages to one or more slave MSC8102 devices on TDM channel 0. Each
slave MSC8102 device transmits back on a different TDM channel with a value that equals its CHIP_ID
value. For example, the boot master transmits a block of data on channel 0. The MSC8102 device with
CHIP_ID = 1 transmits back an acknowledge message on channel 1. The
on the rising edge of
receive channel 0 is enabled. The other channels remain disabled. Also, the MSC8102 transmit channel
CHIP_ID is enabled since this channel is used to transmit messages back to the boot master device. In
this example, the MSC8102 is configured to have a CHIP_ID = 3, so transmit channel 3 is active. These
channels are activated in the TDM3 Receive Channel Parameter Register (TDM3RCPR_n) and the
TDM3 Transmit Channel Parameter Register (TDM3TCPR_n).
Sync sampled
Data driven
Sync sampled
Channel N
Channel N
Freescale Semiconductor, Inc.
Dn
Dn
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D0
DO D1
Channel 0
PORESET
D1
Figure 4. Transmit Frame
Figure 3. Receive Frame
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D2 D3
Channel 0
. Since the boot master transmits messages on channel 0, the MSC8102
Dn
Half Cycle Sync Delay
D4
D0
One Cycle Sync Delay
Channel 1
D5 D6 D7
D1
Dn
Dn
D0
D1
DO
Channel N
Channel N
CHIP_ID[0–3]
Dn D0
Dn DO
Channel 0
Channel 0
pins are sampled
D1 D2 D3
D1
Dn