AN2442 Freescale Semiconductor / Motorola, AN2442 Datasheet - Page 16

• Manufacturer Part Number: AN2442
• Description: Booting the MSC8102 Device Through TDM
• Manufacturer: Freescale Semiconductor / Motorola

Example Boot Master Code
16
; -------------------------------------------
; Set up MCC Global Parameters
; -------------------------------------------
; -------------------------------------------
; Set up Channel Extra Parameters
; RxBD Ch 0 RBASE = MCCBASE + 8 * 0
; RxBD Ch 1 RBASE = MCCBASE + 8 * 1
; RxBD Ch 2 RBASE = MCCBASE + 8 * 2
; RxBD Ch 3 RBASE = MCCBASE + 8 * 3
; TxBD Ch 0 TBASE = MCCBASE + 8 * 4
; TxBD Ch 1 TBASE = MCCBASE + 8 * 5
; TxBD Ch 2 TBASE = MCCBASE + 8 * 6
; TxBD Ch 3 TBASE = MCCBASE + 8 * 7
; -------------------------------------------
_loop_extra_param
write_l #RINTBASE0_CNFG,MCC1_RINTBASE0
write_l #RINTBASE1_CNFG,MCC1_RINTPTR1
write_l #RINTBASE2_CNFG,MCC1_RINTBASE2
write_l #RINTBASE2_CNFG,MCC1_RINTPTR2
nop
bf _loop_cpcr
write_l #MCCBASE_CNFG,MCC1_MCCBASE
write_w #$0,MCC1_STATE
write_w #MCC1_MRBLR_CNFG,MCC1_MRBLR
write_w #$0,MCC1_GRFTHR
write_w #$0,MCC1_GRFCNT
write_l #$0,MCC1_RINTTMP
write_l #$0,MCC1_DATA0
write_l #$0,MCC1_DATA1
write_l #TINTBASE_CNFG,MCC1_TINTBASE
write_l #TINTBASE_CNFG,MCC1_TINTPTR
write_l #$0,MCC1_TINTTMP
write_w #$0,MCC1_SCTBASE
write_w #XTRBASE_CNFG,MCC1_XTRABASE
write_w #0,MCC1_C_MASK16
write_l #$0,MCC1_RINTTMP0
write_l #$0,MCC1_RINTTMP1
write_l #$0,MCC1_RINTTMP2
write_l #$0,MCC1_RINTTMP3
write_l #RINTBASE0_CNFG,MCC1_RINTPTR0
write_l #RINTBASE1_CNFG,MCC1_RINTBASE1 ; Rx interr queue 1 base addr
write_l #RINTBASE3_CNFG,MCC1_RINTBASE3 ; Rx interr queue 3 base addr
write_l #RINTBASE3_CNFG,MCC1_RINTPTR3
move.l #RNUM_CH,d1
move.l #$8,d2
clr d0
move.l #(DPRAM1+XTRBASE_CNFG),d3
imac d0,d2,d3
move.l d3,r0
add d0,d1,d4
move.w d4,(r0)+
move.w d4,(r0)+
move.w d0,(r0)+
move.w d0,(r0)+
cmpeq d0,d1
inc d0
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
; Pointer to BD tables in DPRAM
; Reserved
; Max rx buffer size
; Use only for HDLC
; Use only for HDLC
; Used by the CP
; Used by the CP
; Used by the CP
; Tx interrupt queue base address
; Must point to TINTBASE
; Clear before enabling interrupts
; Superchannel table - not used
; Extra paramter base address
; CRC-16
; Clear before enabling interrupts
; Clear before enabling interrupts
; Clear before enabling interrupts
; Clear before enabling interrupts
; Rx interr queue 0 base addr
; Must point to RINTBASE0
; Must point to RINTBASE1
; Rx interr queue 2 base addr
; Must point to RINTBASE2
; Must point to RINTBASE3