RTL8181 ETC, RTL8181 Datasheet - Page 42

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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CONFIDENTIAL
ENCS1
ENMARP
-
CBSSID
APWRMGT Accept Power Management Packet: This bit will determine whether the RTL8181 will
ADD3
AMF
ACF
ADF
-
RXFTH2, 1,
0
AICV
-
MXDMA2, 1,
0
-
ACRC32
Enable Carrier Sense Detection Method 1
Enable MAC Autoreset PHY
Reserved
Check BSSID, To DS, From DS Match Packet: When set to 1, the RTL8181 will check the
Rx data type frame’s BSSID, To DS and From DS fields, according to NETYPE (bits 3:2,
MSR), to determine if it is set to Link ok at an Infrastructure or Adhoc network.
accept or reject packets with the power management bit set.
1: Accept
0: Reject
Accept Address 3 Match Packets: Set this bit to 1 to accept broadcast/multicast data type
frames that Address 3 matching RTL8181’s MAC address. This bit is valid only when
NETYPE (bits 3:2, MSR) is set to Link ok in an Infrastructure network.
Accept Management Frame: This bit will determine whether the RTL8181 will accept or
reject a management frame.
1: Accept
0: Reject
Accept Control Frame: This bit will determine whether the RTL8181 will accept or reject a
control frame.
1: Accept
0: Reject
Accept Data Frame: This bit will determine whether the RTL8181 will accept or reject a
data frame.
1: Accept
0: Reject
Reserved
Rx FIFO Threshold: This bit specifies the Rx FIFO Threshold level. When the number of
the received data bytes from a packet, which is being received into the Rx FIFO of the
RTL8181, has reached to this level (or the FIFO has contained a complete packet), the
receive PCI bus master function will begin to transfer the data from the FIFO to the ho st
memory. This field sets the threshold level according to the following table:
000: Reserved
001: Reserved
010: 64 bytes
011: 128 bytes
100: 256 bytes
101: 512 bytes
110: 1024 bytes
111: No Rx threshold. The RTL8181 begins the transfer of data after havi ng received a
whole packet into the FIFO.
Accept ICV Error Packet: This bit determines whether all packets with ICV error will be
accepted or rejected.
1: Accept
0: Reject
Reserved
Max DMA Burst Size per Rx DMA Burst: This field sets the maximum size of the receive
DMA data bursts according to the following table:
000: 16 bytes
001: 32 bytes
010: 64 bytes
011: 128 bytes
100: 256 bytes
101: 512 bytes
110: 1024 bytes
111: Unlimited
Reserved
Accept CRC32 Error Packet: When set to 1, all packets with CRC32 error will be accepted.
When set to 0, all packets with CRC32 error will be rejected.
1: Accept
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RTL8181
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
v1.0