RTL8181 ETC, RTL8181 Datasheet - Page 8

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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ANTSELP O
ANTSELN X
TRSWP
TRSWN
VCOPDN/
PHITXI
PAPE
PE1/PHIT
XQ
PE2
RXIP
RXIN
RXQP
RXQN
RSSI
TXDET
VREFI
TXIP
TXIN
TXQP
TXQN
TXAGC
RXAGC
RF Interface for Philip
RIFSCK
RIFSD
RFLE
IFLE/AGC
SET
CALEN/
AGCRESE
T
LNA_HL
ANTSELP O
ANTSELN O
TRSWP
CONFIDENTIAL
X
X
O/I 81
O
O
O
AI*
X
AI
X
X
AI
AI
AO 97
AO 96
AO 94
AO 93
AO 91
AO 90
O
O
O
I
O
X*
O
75
76
78
79
82
84
85
110
109
106
105
103
102
101
66
67
68
70
71
73
75
76
78
M20
L18
L19
L20
K20
K19
K18
J20
B19
B20
C18
C19
D17
D18
C20
E19
F18
E20
F20
F19
G18
R20
P19
P18
N18
P20
M19
M20
L18
L19
Antenna Select +: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSEL- for differential drive of
antenna switches.
Not used in the RFMD RF chipset.
Not used in the RFMD RF chipset.
Not used in the RFMD RF chipset.
Output Pin as VCO VCC Power Enable/Disable.
Power Control Output for RF2189 PA: 0V to +3.3V.
This pin is the shutdown control output on board regulator when the RF Module
enters either power-saving or standby mode.
Output pin as RF2948 RX EN/ TX EN, RF2494 OE and CE:
Refer to the RF2948 and RF2494 datasheets.
Receive (Rx) In-phase Analog Data in Single Ended
Not used in RFMD RF chipset.
Receive (Rx) Quadrature-phase Analog Data in Single Ended
Not used in RFMD RF chipset.
Not used in RFMD RF chipset.
To internal ADC which detects transmit power.
Reference voltage for ADC, DAC from VREF1 of RF2948B.
Transmit (TX) In-phase Digital Data: Combining before connecting to TX_I of
RF2948B.
Transmit (TX) Quadrature Digital Data: Combining before connecting to TX_Q
of RF2948B.
Transmit gain control output to RF2948.
RF2948 VGC receiver gain control analog output.
3-wire Bus Clock: The pin RIFSCK is the “shift clock” output. If the 3-wire bus
is enabled, address or data bits will be clocked out from the RIFSD pin with
rising edges of RIFSCK.
3-wire Bus Data: The pin RIFSD is the output “data” pin. The detail timing is on
11.3.3.
3-wire Bus Enable: The pin RFLE is an “enable” signal. It is level sensitive: If
RFLE is of LOW value, the 3-wire bus interface on the SA2400 is enabled. This
means that each rising edge on the RIFSCK pin will be taken as a shift cycle,
and address/data bits are expected on RIFSD. If RFLE is HIGH, the 3-wire bus
interface is disabled. No register settings will change regardless activity on
RIFSCK and RIFSD.
AGCSET of the Philips Chipset: On the digital output pin AGCRESET, a 0 => 1
transition clears AGCSET of SA2400 to logic 0 and SA2400 starts the AGC
cycle. At end of AGC cycle, the AGCSET of SA2400 is asserted to logic 1. Then,
AGCRESET will return to logic low.
AGCRESET of the Philips Chipset: Please refer to the AGCSET description and
Philips SA2400 datasheet.
Not used in Philips RF chipset.
Antenna Select +: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSEL- for differential drive of
antenna switches.
Antenna Select -: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSEL+ for differential drive of
antenna switches.
Transmit and Receive Switch Control: This is a complement for TRSW-.
1:TX
0:RX
8
RTL8181
v1.0