RTL8181 ETC, RTL8181 Datasheet - Page 7

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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WLTXRX
LED1B
RF Interface for Intersil
RIFSCK
RIFSD
RFLE
IFLE/AGC
SET
CALEN/
AGCRESE
T
LNA_HL O
ANTSELP O
ANTSELN O
TRSWP
TRSWN
VCOPDN/
PHITXI
PAPE
PE1/PHIT
XQ
PE2
RXIP
RXIN
RXQP
RXQN
RSSI
TXDET
VREFI
TXIP
TXIN
TXQP
TXQN
TXAGC
RXAGC
RF Interface for RFMD
RIFSCK
RIFSD
RFLE
IFLE/AGC
SET
CALEN/
AGCRESE
T
LNA_HL O
CONFIDENTIAL
O
O
O
O
O
O
O
O
O
O
O
O
AI
AI
AI
AI
AI
AI
AI
AO
AO
AO
AO
AO 91
AO 90
O
O
O
X*
X
64
66
67
68
70
71
73
75
76
78
79
81
82
84
85
110
109
106
105
102
101
97
96
94
93
66
67
68
70
71
73
T18
R20
P19
P18
N18
P20
M19
M20
L18
L19
L20
K20
K19
K18
J20
B19
B20
C18,C19
D17
D18
C20
E19,F18
E20,F20
F19
G18
R20
P19
P18
N18
P20
M19
WLAN Tx/Rx traffic indicator or JTAG CLK
3-wire Bus Clock
3-wire Bus Data
3-wire Bus Enable
IF_LE of the Intersil Chipset: PLL Synthesizer Serial Interface Latch Enable
Control. CMOS output.
CAL_EN of the Intersil Chipset: CMOS output for activation of DC offset adjust
circuit. A rising edge activates the calibration cycle, which completes within a
programmable time and holds the calibration while this pin is held high. In
applications where the synthesizer is not used, this pin needs to be grounded.
Drive to the RF AGC Stage Attenuator: CMOS digital.
Antenna Select +: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSELN for differential drive of
ant enna switches.
Antenna Select -: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSELP for differential drive of
antenna switches.
Transmit/Receive Control
Output Pin as VCO VCC Power Enable/Disable.
Transmit PA Power Enable
The combination of PE1 and PE2 are as follows:
00: Power Down State, PLL Registers in Save Mode, Inactive PLL, Active Serial
11: Receive State, Active PLL
10: Transmit State, Active PLL
01: Inactive Transmit and Receive States, Active PLL, Active Serial Interface
Output Pin as PE2: Refer to PE1 description.
Receive (Rx) In-phase Differential Analog Data
Receive (Rx) Quadrature Differential Analog Data
Analog Input to the Receive Power A/D Converter for AGC Control
Input to the Transmit Power A/D Converter for Transmit AGC Control
Voltage Reference for ADC and DAC
Transmit (TX) In-phase Differential Analog Data
Trans mit (TX) Quadrature Differential Analog Data
Analog Drive to the Transmit IF Power Control
Analog Drive to the Receive IF AGC Control
3-wire Bus Clock: The serial clock output, with resistive dividers on board to
allow programming from +5V levels.
3-wire Bus Data: Serial data output, with resistive dividers on board to allow
programming from +5V levels.
3-wire Bus Enable: Enable serial port output, with resistive dividers on board to
allow programming from +5V levels.
Not used in the RFMD RF chipset.
Not used in the RFMD RF chipset.
RF2494 Gain Select: Digital output.
7
RTL8181
v1.0