RTL8181 ETC, RTL8181 Datasheet - Page 43

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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4
3
2
1
0
Command Register (WLAN_CR)
This register is used for issuing commands to the WLAN controller. These commands are issued by setting the corresponding bits
for the function. A warm software reset along with individual reset and enable/disable for transmitter and receiver are provided as
well.
Configuration Register 0 (WLAN_CONFIG0)
Configuration Register 2 (WLAN_CONFIG2)
CONFIDENTIAL
Bit
7-6
5-0
Bit
7-4
3
2
1-0
Bit
7
6
5-4
3
2
1-0
-
AB
AM
APM
AAP
Bit Name
EEM
-
Bit Name
-
Aux_Status
-
GL
Bit Name
LCK
ANT
-
DPS
PAPE_sign
PAPE_time
0: Reject
Reserved
Accept Broadcast Packets: This bit determines whether broadcast packets will be accepted
or rejected.
1: Accept
0: Reject
Accept Multicast Packets: This bit determines whether multicast packets will be accepted or
rejected.
1: Accept
0: Reject
Accept Physical Match Packets: This bit determines whether physical match packets will be
accepted or rejected.
1: Accept
0: Reject
Accept Destination Address Packets: This bit determines whether all packets with a
destination address will be accepted or rejected.
1: Accept
0: Reject
Description
These 2 bits select the operating mode.
00: Operating in network/host communication mode.
11: Before writing to the WLAN_CONFIG0, 1, 2, and 3 registers, the RTL8181 must be
placed in this mode. This will prevent accidental change of the configurations of the WLAN
controller.
Reserved
Description
Reserved
Auxiliary Power Present Status: This bit indicates the existence of Aux. power. The value of
this bit is fixed after each reset.
1: Aux. Power is present
0: Aux. Power is absent
Reserved
Geographic Location: These bits indicate the current operational region in which RTL8181
transmits and receives packets..
USA: 11, Europe: 10, Japan: 0
Description
Locked Clocks: Set this bit to 1 to indicate that the transmit frequency and symbol clocks are
derived from the same oscillator.
Antenna Diversity:
1: Enable
0: Disable
Reserved
Descriptor Polling State: Test mode..
0: Normal working state. This is also the power-on default value.
1: Test Mode
1: RTL8181 will advance PAPE_time to enable the PAPE pin when Tx data
0: RTL8181 will delay PAPE_time to enable the PAPE pin when Tx data
These two bits indicate that the RTL8181 has enabled the PAPE pin in µs.
43
RTL8181
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
v1.0