RTL8181 ETC, RTL8181 Datasheet - Page 46

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

www.DataSheet4U.com
Default Key 3 Register (WLAN_DK3)
Configuration Register 5 (WLAN_CONFIG5)
This register, unlike other Configuration registers, is not protected by the Command register. Therefore, there is no need to
enable the Config register write prior to writing to Config5.
Transmit Priority Polling Register (WLAN_TPPOLL)
CONFIDENTIAL
Bit
127-104 -
103-0
Bit
7
6
5
4-0
Bit
7
6
5
4
Bit Name
TX_FIFO_OK Built in Self Test for TX FIFO:
RX_FIFO_OK Built in Self Test for RX FIFO:
CALON
-
Bit Name
BQ
HPQ
NPQ
LPQ
Bit Name Description
DK3
Reserved
Default Key 3: These 104 bits (bits 103:0) indicate the default 104-bit WEP key, which the ID
is 3 when KM (bits 5:4, SCR) is set to WEP104, the 24 most significant bits (bits 127:103)
will be reserved. The 40 least significant bits (bits 39:0) indicate the default 40-bit WEP key,
which the ID is 3 when KM is set to WEP40, and the 64 most significant bits (bits 103:40) will
be reserved.
This register is only permitted to read/write by 4-byte access.
ID is 2 when KM (bits 5:4, SCR) is set to WEP104, the 24 most significant bits (bits
127:103) will be reserved. The 40 least significant bits (bits 39:0) indicate the default 40-bit
WEP key, which the ID is 2 when KM is set to WEP40, and the 64 most significant bits (bits
103:40) will be reserved. This register is only permitted to read/write by 4-byte access.
Description
1: OK
0: Fail
1: OK
0: Fail
Calibration ON.
1: Activate the calibration cycle, and hold AGCRESET pin to high
0: Put AGCRESET pin to ground
Reserved
Description
Beacon Queue Polling:
The RTL8181 will clear this bit automatically after a beacon packet has been transmitted or
received.
Writing to this bit has no effect.
High Priority Queue Polling:
Write a 1 to this bit by software to notify the RTL8181 that there is a high priority packet(s)
waiting to be transmitted.
The RTL8181 will clear this bit automatically after all high priority packets have been
transmitted.
Writing a 0 to this bit has no effect.
Normal Priority Queue Polling:
DPS (bit3, Config 2) set to 0:
The RTL8181 will clear this bit automatically after all normal priority packets have been
transmitted or received.
Writing to this bit has no effect.
DPS (bit3, Config 2) set to 1:
Write a 1 to this bit by software to notify the RTL8181 that there is a normal priority
packet(s) waiting to be transmitted.
The RTL8181 will clear this bit automatically after all normal priority packets have been
transmitted.
Writing a 0 to this bit has no effect.
Low Priority Queue Polling:
Write a 1 to this bit by software to notify the RTL8181 that there is a low priority packet(s)
waiting to be transmitted.
The RTL8181 will clear this bit automatically after all low priority packets have been
transmitted.
Writing a 0 to this bit has no effect.
46
RTL8181
R/W
-
R/W
R/W
R
R
R/W
-
R/W
W
W
W
W
v1.0