RTL8181 ETC, RTL8181 Datasheet - Page 48

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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Packet Buffering
RTL8181 WLAN controller incorporates two independent FIFOs for transferring data to/from the system interface and from/to
the network. The FIFOs, providing temporary storage of data freeing the host system from the real - time demands of the
network.
The way in which the FIFOs are emptied and filled is controlled by the FIFO threshold values in the Receive Configuration
registers. These values determine how full or empty the FIFOs must be before the device requests the bus. Once RTL8181
requests the bus, it will attempt to empty or fill the FIFOs as allowed by the respective MXDMA settings in the Transmit
Configuration and Receive Configuration registers.
Transmit Buffer Manager
The buffer management scheme used on the WLAN controller allows quick, simple and efficient use of the frame buffer
memory. The buffer management scheme uses separate buffers and descriptors for packet information. This allows effective
transfers of data to the transmit buffer manager by simply transferring the descriptor information to the transmit queue.
The Tx Buffer Manager DMAs packet data from system memory and places it in the 4KB transmit FIFO, and pulls data from
the FIFO to send to the Tx MAC. Multiple packets may be present in the FIFO, allowing packets to be transmitted with short
interframe space. Additionally, once RTL8181 requests the bus, it will attempt to fill the FIFO as allowed by the MXDMA
setting.
The Tx Buffer Manager process also supports priority queuing of transmit packets. It handles this by drawing from two
separate descriptor lists to fill the internal FIFO. If packets are available in the high priority queues, they will be loaded into
the FIFO before those of low priority.
Receive Buffer Manager
The Rx Buffer Manager uses the same buffer management scheme as used for transmits. The Rx Buffer Manager retrieves
packet data from the Rx MAC and places it in the 2KB receive data FIFO, and pulls data from the FIFO for DMA to system
memory. The receive FIFO is controlled by the FIFO threshold value in RXFTH. This value determines the number of long
words written into the FIFO from the MAC unit before a DMA req uest for system memory occurs. Once the RTL8181 gets the
bus, it will continue to transfer the long words from the FIFO until the data in the FIFO is less than one long word, or has
reached the end of the packet, or the max DMA burst size is reached, as se t in MXDMA.
13. Package Information
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CONFIDENTIAL
KeyMapOp
KeyMapPoll Polling bit of read/write key.
-
‘0’ implies the entry is invalid.
Operation for writing or reading key value. Value ‘1’ indicates to set key value, ‘0’ means to
get key value.
1.
2.
3.
Reserved
Set ‘1’ to make RTL8181 begin to read/write the value of key table, which entry
index is specified in KeyMapIdx.
RTL8181 will clear the bit atomically after the operation is completed.
Writing ‘0’ to this bit has no effect.
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RTL8181
R/W
R/W
v1.0
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