MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 105

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

Data Sheet
Bit
7
6
5
4
3
2
Table 148 - HDLC Interrupt Status Register
TxUNDER
RxEOP
TxEOP
Name
RxFE
TXFL
FA:
GA
(Page B & C, Address 17H)
Go Ahead. Indicates a go-
ahead pattern was detected by
the HDLC receiver. This bit is
reset after a read.
End Of Packet Detected. This
bit is set when an end of packet
(EOP) byte was written into the
RX FIFO by the HDLC receiver.
This can be in the form of a flag,
an abort sequence or as an
invalid packet. This bit is reset
after a read.
Transmit End Of Packet. This
bit is set when the transmitter
has finished sending the closing
flag of a packet or after a packet
has been aborted. This bit is
reset after read.
End Of Packet Read. This bit is
set when the byte about to be
read from the RX FIFO is the last
byte of the packet. It is also set if
the Rx FIFO is read and there is
no data in it. This bit is reset after
a read.
TX FIFO Low. This bit is set
when the Tx FIFO is emptied
below
threshold level. This bit is reset
after a read.
Frame Abort/TX FIFO Under-
run.When Intsel bit of Control
Register 2 is low, this bit (FA) is
set when a frame abort is re-
ceived during packet reception.
It must be received after a mini-
mum number of bits have been
received (26) otherwise it is ig-
nored.
When INTSEL bit of Control
Register 2 is high, this bit is set
for
indication. If high it Indicates
that a read by the transmitter
was attempted on an empty Tx
FIFO.
This bit is reset after a read.
Functional Description
a
TX
the
FIFO
selected
underrun
low
Bit
7-0 CRC1
7-0 CRC7-0 The LSB byte of the CRC received
Bit Name
Bit
1
0
Table 148 - HDLC Interrupt Status Register
Table 149 - Receive CRC MSB Register
Table 150 - Receive CRC LSB Register
Name
5-8
RxOVF
Name
RXFF
(Page B & C, Address 18H)
(Page B & C, Address 19H)
(Page B & C, Address 17H)
The MSB byte of the CRC received
from the transmitter. These bits are
as the transmitter sent them; that is,
most significant bit first and inverted.
This register is updated at the end of
each received packet and therefore
should be read when end of packet is
detected.
from the transmitter. These bits
are as the transmitter sent them;
that is, most significant bit first and
inverted. This register is updated at
the end of each received packet and
therefore should be read when end
of packet is detected.
RX FIFO Full. This bit is set
when the Rx FIFO is filled
above the selected full threshold
level. This bit is reset after a
read.
RX FIFO Overflow. Indicates
that the 128 byte RX FIFO
overflowed (i.e. an attempt to
write to a 128 byte full RX
FIFO). The HDLC will always
disable the receiver once the
receive
detected. The receiver will be
re-enabled upon detection of
the next flag, but will overflow
again unless the RX FIFO is
read. This bit is reset after a
read.
Functional Description
Functional Description
Functional Description
overflow
MT9074
has
been
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