MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 26

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
26
Interframe Time Fill and Link Channel States
When the HDLC transmitter is not sending packets it
will wait in one of two states
•
•
In both states the transmitter will exit the wait state
when data is loaded into the transmitter FIFO.
Go-Ahead
A go ahead is defined as the pattern "011111110"
(contiguous 7Fs) and is the occurrence of a frame
abort sequence followed by a zero, outside of the
boundaries of a normal packet. Being able to
distinguish a proper (in packet) frame abort
sequence from one occurring outside of a packet
allows a higher level of signaling protocol which is
not part of the HDLC specifications.
HDLC Functional Description
The HDLC transceiver can be reset by either the
power reset input signal or by the HRST Control bit
in the test control register (software reset). When
reset, the HDLC Control Registers are cleared,
resulting in the transmitter and receiver being
disabled. The Receiver and Transmitter can be
enabled independent of one another through Control
Register 1. The transceiver input and output are
enabled when the enable control bits in Control
Register 1 are set. Transmit to receive loopback as
well as a receive to transmit loopback are also
supported. Transmit and receive bit rates and
enables can operate independently. In MT9074 the
transceiver can operate at a continuous rate
independent of RXcen and TXcen (free run mode) by
setting the Frun bit of Control Register 1.
Received packets from the serial interface are
sectioned into bytes by an HDLC receiver that
detects flags, checks for go-ahead signals, removes
inserted zeros, performs a cyclical redundancy
check (CRC) on incoming data, and monitors the
address if required. Packet reception begins upon
detection of an opening flag. The resulting bytes are
concatenated with two status bits (RQ9, RQ8) and
placed in a receiver first-in-first-out (Rx FIFO); a
buffer register that generates status and interrupts
for microprocessor read control.
Interframe Time Fill state: This is a continuous
series of flags occurring between frames
indicating that the channel is active but that no
data is being sent.
Idle state: An idle Channel occurs when at least
15 contiguous 1s are transmitted or received.
In
microprocessor writes data bytes into a Tx buffer
register (Tx FIFO) that generates status and
interrupts. Packet transmission begins when the
microprocessor writes a byte to the Tx FIFO. Two
status bits are added to the Tx FIFO for transmitter
control of frame aborts (FA) and end of packet (EOP)
flags. Packets have flags appended, zeros inserted,
and a CRC, also referred to as frame checking
sequence (FCS), added automatically during serial
transmission. When the Tx FIFO is empty and
finished sending a packet, Interframe Time Fill bytes
(continuous flags (7E hex)), or Mark Idle (continuous
ones) are transmitted to indicate that the channel is
idle.
HDLC Transmitter
Following initialization and enabling, the transmitter
is in the Idle Channel state (Mark Idle), continuously
sending ones. Interframe Time Fill state (Flag Idle) is
selected by setting the Mark idle bit in Control
Register 1 high.
NOTE: If the MT9074A HDLC transmitter is set up
in the Interframe Time Fill state (bit 2, Mark-
Idle=1, page B or C, address 13H), then it will
occasionally (less than 1% of the time) fail to
transmit the opening flag when it is changed
from the disabled state to the enabled state (bit 5
TxEN changed from 0 to1). A missing opening
flag will cause the packet to be lost at the
receiving end.
This problem only affects the first packet
transmitted
enabled. Subsequent packets are unaffected.
The Transmitter remains in either of these two states
until data is written to the Tx FIFO. Control Register
1 bits EOP (end of packet) and FA (Frame Abort) are
set as status bits before the microprocessor loads 8
bits of data into the 10 bit wide FIFO (8 bits data and
2 bits status). To change the tag bits being loaded in
the FIFO, Control Register 1 must be written to
before writing to the FIFO. However, EOP and FA
are reset after writing to the TX FIFO. The Transmit
Byte Count Register may also be used to tag an end
of packet. The register is loaded with the number of
bytes in the packet and decrements after every write
to the Tx FIFO. When a count of one is reached, the
next byte written to the FIFO is tagged as an end of
packet. The register may be made to cycle through
the same count if the packets are of the same length
by setting Control Register 2 bit Cycle.
If the transmitter is in the Idle Channel state when
data is written to the Tx FIFO, then an opening flag is
sent and data from Tx FIFO follows. Otherwise, data
bytes are transmitted as soon as the current flag
conjunction
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