MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 106

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
106
7-0s TxCNT
Bit
Bit
7
6
5
4
Table 151 - Transmit Byte Count Register
Table 152 - HDLC Test Control Register
RTLOOP
Name
Name
HRST
7-0
RSV
RSV
(Page B & C, Address 1AH)
(Page B & C, Address 1BH)
Transmit Byte Count Register. The
Transmit
indicating the length of the packet
about to be transmitted. When this
register reaches the count of one, the
next write to the Tx FIFO will be
tagged as an end of packet byte. The
counter decrements at the end of the
write to the Tx FIFO. If the Cycle bit
of Control Register 2 is set high, the
counter
programmed value continuously.
HDLC Reset. When this bit is set
to one, the HDLC will be reset.
This is similar to RESET being
applied, the only difference being
that this bit will not be reset. This
bit can only be reset by writing a
zero twice to this location or
applying RESET.
RT Loopback. When this bit is
high, receive to transmit HDLC
loopback
Receive data, including end of
packet
including flags or CRC, will be
written to the TX FIFO as well as
the
transmitter is enabled, this data
will be transmitted as though
written by the microprocessor.
Both good and bad packets will
be looped back. Receive to
transmit loopback may also be
accomplished by reading the RX
FIFO using the microprocessor
and writing these bytes, with
appropriate tags, into the TX
FIFO.
Reserved. Must be set to 0 for
normal operation.
Reserved. Must be set to 0 for
normal operation.
Functional Description
Functional Description
RX
will
Byte
indication,
will
cycle
FIFO.
Count
be
through
When
activated.
but
Register
not
the
the
Bit
3
2
1
0
Table 152 - HDLC Test Control Register
CRCTST
HLOOP
ARTST
Name
FTST
(Page B & C, Address 1BH)
CRC Remainder Test. This bit
allows direct access to the CRC
Comparison
receiver
interface. After testing is enabled,
serial data is clocked in until the
data aligns with the internal
comparison
cycles) and then the clock is
stopped. The expected pattern is
F0B8 hex. Each bit of the CRC
can be corrupted to allow more
efficient testing.
FIFO Test. This bit allows the
writing to the RX FIFO and
reading of the TX FIFO through
the microprocessor to allow more
efficient testing of the FIFO
status/interrupt functionality. This
is done by making a TX FIFO
write become a RX FIFO write
and a RX FIFO read become a
TX FIFO read. In addition, EOP/
FA and RQ8/RQ9 are re-defined
to be accessible (i.e. RX write
causes EOP/FA to go to RX fifo
input; TX read looks at output of
TX fifo through RQ8/RQ9 bits).
Address Recognition Test. This
bit allows direct access to the
Address Recognition Registers in
the receiver through the serial
interface to allow more efficient
testing. After address testing is
enabled, serial data is clocked in
until the data aligns with the
internal address comparison (16
RXc clock cycles) and then clock
is stopped.
TR
transmit
loopback will be activated. The
packetized transmit data will be
looped back to the receive input.
RXEN and TXEN bits must also
be enabled.
Functional Description
Loopback.
through
to
(16
Register
receive
Data Sheet
When
RXC
the
in
HDLC
serial
clock
high,
the