MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 81

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

Data Sheet
6-5
Bit
7
4
3
2
1
0
Table 96 - Configuration Control Word
ADSEQ Digital Milliwatt or Digital Test
LIUEn
Name
T1/E1
ELOS
RSV
RSV
RSV
(Page 2, Address 10H) (E1)
E1 Mode Selection. when this bit is
one, the device is in E1 mode.
Reserved. Must be kept at 0 for
normal operation.
LIU Enable.Setting this bit low
enables the internal LIU front-end.
Setting this pin high disables the
LIU. Digital inputs RXA and RXB are
sampled by the rising edge of E2.0i
(C1.50) to strobe in the received line
data. Digital transmit data is clocked
out of pins TXA and TXB with the
rising edge of C2.0o
ELOS Enable. Set this bit low to set
the analog loss of signal threshold to
40 dB below nominal. Set this bit
high to set the analog loss of signal
threshold to 20 dB below nominal.
Reserved. Must be kept at 0 for
normal operation.
Sequence. If one, the A-law digital
milliwatt analog test sequence will
be selected by the Per Time Slot
Control bits TTST and RTST.If zero,
a PRBS generator / detector will be
connected to channels with TTST,
RRST respectively
Reserved. Must be kept at 0 for
normal operation.
Functional Description
6-4
2-0
6-0 CP6-0 Custom Pulse. These bits provide the
Bit
Bit
7
3
7
Name
Name
RSV
RSV
RSV
RSV
CPL
Table 97 - Custom Tx Pulse Enable
Table 98 - Custom Pulse Word 1
(Page 2, Address 1CH) (E1)
(Page 2, Address 11H) (E1)
Reserved. Must be kept high for
normal operation.
Reserved. Must be kept low for normal
operation.
Custom Pulse Level. Setting this bit
low enables the internal ROM values in
generating the transmit pulses. The
ROM
terminations or build out, as specified
in the LIU Control word. Setting this bit
high disables the pre-programmed
pulse templates. Each of the 4 phases
that generate a mark derive their D/A
coefficients
programmed in the CPW registers.
Reserved. Must be kept at 0 for normal
operation.
Reserved. Must be kept at 0 for normal
operation.
capability
magnitude setting for the TTIP/TRING
line driver A/D converter during the first
phase of a mark. The greater the
binary number loaded into the register,
the greater the amplitude driven out.
This feature is enabled when the
control bit 3 - CPL of the Custom Tx
Pulse Enable Register - address 11H
of Page 2 is set high.
Functional Description
Functional Description
is
coded for
for
from
programming
the
MT9074
different line
values
the
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