MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 42

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
42
Interrupts on T1 Mode
Interrupt Mask Word Zero
Bit 7
Interrupt Mask Word One
Bit 7
Interrupt Mask Word Two
Bit 7
Interrupt Mask Word Three
Bit 7
HDLC Interrupt Masks
Bit 7
Interrupts on E1 Mode
Interrupt Mask Word Zero
Bit 7
Interrupt Mask Word One
Bit 7
Interrupt Mask Word Two
Bit 7
Interrupt Mask Word Three
Bit 7
HDLC Interrupt Masks
Bit 7
TFSYNI MFSYNI TSAI
FEO CRCO OOFO COFAO BPVO PRBSO MFOOFO - - -
FEOM
SYNI
FERI
FEI
- - -
- - -
Ga
Ga
MFSYI
CRCI
CRCO
EOPD TEOP
CRCI
EOPD TEOP
- - -
- - -
YELI
EBI
CSYNI
EBOI
- - -
- - -
COFAI
AIS16I
EopR
EopR
- - -
LCDI
JAI
AISI
AISI
BPVO PRBSO PRBSMO
1SECI 5SECI RCRI
1SECI 5SECI BIOMI
LOSI
BPVI
BPVI
TxFl
TxFl
LOSI
FATxU
FATxU
SEI
PRBSI
PRBSI AUXPI
CEFI
TxSLPI
RxFf
RxFf
PDVI
YI
Bit 0
Bit 0
RxSLPI
RxOv
RxOv
SLPI
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
SIGI
Bit 0
SIGI
RAII
- - -
- - -
Digital Framer Mode
T1 Mode
Setting bit 4 in the Configuration Control Word
(address 10H of Master Control Page 2) disables the
LIU and converts the MT9074 into a digital T1
transceiver.
backplane maps into transmit and receive digital
1.544 Mb/s streams. The 1.544 Mb/s transmit
streams may be formatted for single phase NRZ (by
setting bit 7 of the LIU Control Word - Master Page 1
high) or two phase NRZ. The data rate conversion
(between 2.048 Mb/s and 1.544 Mb/s) is done within
the MT9074. The transmit 1.544 MHz clock is
internally generated from a PLL that locks onto the
input C4b clock. This clock is then output on pin
E1.5o (PLCC pin 44 - QFP pin 32). The digital 1.544
Mb/s transmit data is output on pins TXA and TXB
(PLCC pins 37,38 - QFP pins 18,19) with the rising
edge of C1.5o. Receive digital data is clocked in on
pins RRING and RTIP. This data is clocked in with
the rising edge of the input 1.544 Mhz clock S/FR/
E1.5i (PLCC pin 66, QFP pin 63). Coding is optional
under software control.
E1 Mode
Setting bit 4 in the Configuration Control Word
(address 10H of Master Control Page 2) disables the
LIU and converts the MT9074 into a digital E1
transceiver.
backplane maps into transmit and receive digital
2.048 Mb/s streams. The 2.048 Mb/s transmit data
streams may be formatted for single phase NRZ (by
setting bit 7 of the LIU Control Word - Master Page 1
high) or two phase NRZ. The transmit 2.048 MHz
clock is derived from the input C4b clock. This clock
is then output on pin E1.5o (PLCC pin 44 - QFP pin
32). The digital 2.048 Mb/s transmit data is output on
pins TXA and TXB (PLCC pins 37,38 - QFP pins
18,19) with the rising edge of E1.5o. Receive digital
data is clocked in on pins RRING and RTIP. This
data is clocked in with the rising edge of the input
2.048 Mhz clock MS/FR/E1.5i (PLCC pin 66, QFP
pin 63). Coding is optional under software control.
The
The
digital
digital
2.048
2.048
Mb/s
Mb/s
Data Sheet
ST-BUS
ST-BUS