ds265188-port-t1-e1-j1-transc Maxim Integrated Products, Inc., ds265188-port-t1-e1-j1-transc Datasheet - Page 236

• Manufacturer Part Number: ds265188-port-t1-e1-j1-transc
• Description: Ds26518 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are real time.
Bit 3: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Bit 2: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 1: Transmit FIFO Below Low Watermark Condition (TLWM). Set when the transmit 64-byte FIFO empties
beyond the low watermark as defined by the transmit low watermark bits (TLWM).
Bit 0: Transmit FIFO Not Full Condition (TNF). Set when the transmit 64-byte FIFO has at least one byte
available.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 6 to 0: Transmit FIFO Bytes Available (TFBA6 to TFBA0). TFBA0 is the LSB.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit HDLC-64 Data Bit 7 (THD7). MSB of an HDLC-64 packet data byte.
Bit 6: Transmit HDLC-64 Data Bit 6 (THD6)
Bit 5: Transmit HDLC-64 Data Bit 5 (THD5)
Bit 4: Transmit HDLC-64 Data Bit 4 (THD4)
Bit 3: Transmit HDLC-64 Data Bit 3 (THD3)
Bit 2: Transmit HDLC-64 Data Bit 2 (THD2)
Bit 1: Transmit HDLC-64 Data Bit 1 (THD1)
Bit 0: Transmit HDLC-64 Data Bit 0 (THD0). LSB of an HDLC-64 packet data byte.
THD7
—
—
7
0
7
0
7
0
TRTS2
Transmit Real-Time Status Register 2 (HDLC-64)
1B1h + (200h x (n - 1)) : where n = 1 to 8
TFBA
Transmit HDLC-64 FIFO Buffer Available Register
1B3h + (200h x (n - 1)) : where n = 1 to 8
THF
Transmit HDLC-64 FIFO Register
1B4h + (200h x (n - 1)) : where n = 1 to 8
TFBA6
THD6
—
6
0
6
0
6
0
TFBA5
THD5
—
5
0
5
0
5
0
236 of 313
TFBA4
THD4
—
4
0
4
0
4
0
TEMPTY
TFBA3
THD3
3
0
3
0
3
0
DS26518 8-Port T1/E1/J1 Transceiver
TFBA2
TFULL
THD2
2
0
2
0
2
0
TFBA1
TLWM
THD1
1
0
1
0
1
0
TFBA0
THD0
TNF
0
0
0
0
0
0