ds265188-port-t1-e1-j1-transc Maxim Integrated Products, Inc., ds265188-port-t1-e1-j1-transc Datasheet - Page 260

• Manufacturer Part Number: ds265188-port-t1-e1-j1-transc
• Description: Ds26518 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All latched bits in this register can create interrupts.
Bit 7: BERT Receive All-Ones Condition Clear (BRA1C). A latched bit that is set when the BERT transitions out
of all-ones condition.
Bit 6: BERT Receive All-Zeros Condition Clear (BRA0C). A latched bit that is set when the BERT transitions out
of all-zeros condition.
Bit 5: BERT Receive Loss of Synchronization Condition Clear (BRLOSC). A latched bit that is set when the
BERT transitions out of loss of synchronization condition.
Bit 4: BERT in Synchronization Condition Clear (BSYNCC). A latched bit that is set when the BERT transitions
out of synchronization condition.
Bit 3: BERT Receive All-Ones Condition Detect (BRA1D). A latched bit that is set when 32 consecutive ones
are received.
Bit 2: BERT Receive All-Zeros Condition Detect (BRA0D). A latched bit that is set when 32 consecutive zeros
are received.
Bit 1: BERT Receive Loss of Synchronization Condition Detect (BRLOSD). A latched bit that is set whenever
the receive BERT begins searching for a pattern.
Bit 0: BERT in Synchronization Condition Detect (BSYNCD). A latched bit that is set when the incoming pattern
matches for 32 consecutive bit positions.
BRA1C
7
0
BLSR1
BERT Latched Status Register 1
1402h + (10h x (n - 1)) : where n = 1 to 8
BRA0C
6
0
BRLOSC
5
0
BSYNCC
260 of 313
4
0
BRA1D
3
0
DS26518 8-Port T1/E1/J1 Transceiver
BRA0D
2
0
BRLOSD
1
0
BSYNCD
0
0