ds265188-port-t1-e1-j1-transc Maxim Integrated Products, Inc., ds265188-port-t1-e1-j1-transc Datasheet - Page 270

• Manufacturer Part Number: ds265188-port-t1-e1-j1-transc
• Description: Ds26518 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 2: Receive FIFO Full (RFF). When 0, the receive FIFO contains 255 or less bytes of data. When 1, the receive
FIFO is full.
Bit 1: Receive FIFO Empty (RFE). When 0, the receive FIFO contains at least one byte of data. When 1, the
receive FIFO is empty.
Bit 0: Receive HDLC-256 Data Available (RHDA). When 0, the receive FIFO contains less data than the receive
HDLC-256 data available level (RDAL[4:0]). When 1, the receive FIFO contains the same or more data than the
receive HDLC-145 data available level.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive FIFO Overflow Latched (RFOL). This bit is set when a receive FIFO overflow condition occurs. An
overflow condition results in a loss of data.
Bit 4: Receive Packet End Latched (RPEL). This bit is set when an end of packet is stored in the receive FIFO.
Bit 3: Receive Packet Start Latched (RPSL). This bit is set when a start of packet is stored in the receive FIFO.
Bit 2: Receive FIFO Full Latched (RFFL). This bit is set when the RFF bit transitions from 0 to 1.
Bit 0: Receive HDLC-256 Data Available Latched (RHDAL). This bit is set when the RHDA bit transitions from
0 to 1.
RFOL
—
7
0
7
0
—
—
6
0
6
0
RH256SR
Receive HDLC-256 Status Register
1514h+ (20h x (n - 1)) : where n = 1 to 8
RH256SRL
Receive HDLC-256 Status Register Latched
1516h + (20h x (n - 1)) : where n = 1 to 8
—
—
5
0
5
0
270 of 313
RPEL
—
4
0
4
0
RPSL
—
3
0
3
0
DS26518 8-Port T1/E1/J1 Transceiver
RFFL
RFF
2
0
2
0
RFE
—
1
0
1
0
RHDAL
RHDA
0
0
0
0