ds265188-port-t1-e1-j1-transc Maxim Integrated Products, Inc., ds265188-port-t1-e1-j1-transc Datasheet - Page 75

• Manufacturer Part Number: ds265188-port-t1-e1-j1-transc
• Description: Ds26518 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

9.10
There are two HDLC controllers available for each port of the DS26518. HDLC-64 is the default HDLC controller,
which is software compatible to the entire TEX series of SCTs. The HDLC-256 controller is presently only available
on the DS26518 and DS26514. (Note: Older DS26518 die revisions do not have this feature, so check the device
errata.)
Table 9-36. HDLC-64/HDLC-256 Controller Features
9.10.1 HDLC-64 Controller
The DS26518 has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1
mode), or the FDL (T1 mode). This HDLC controller has a 64-byte FIFO buffer in both the transmit and receive
paths. The user can select any specific bits within the time slot(s) to assign to the HDLC-64 controller, as well as
specific Sa bits (E1 mode).
The HDLC-64 controller performs all the necessary overhead for generating and receiving performance report
messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC-64
controller automatically generates and detects flags, generates and checks the CRC checksum, generates and
detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the
HDLC-64 controller are large enough to allow a full PRM to be received or transmitted without host intervention.
Table 9-37
CONTROLLER
HDLC-256
HDLC-64
HDLC
Table 9-36
HDLC Controllers
shows the registers related to the HDLC-64.
describes the features available for each controller.
FIFO DEPTH
(BYTES)
256
64
MAP TO FDL
Yes
Yes
75 of 313
MAP TO
Sa BITS
Yes
Yes
DS26518 8-Port T1/E1/J1 Transceiver
SINGLE DS0
MAP TO
Yes
Yes
Yes, up to 32
MULTIPLE
MAP TO
DS0s
No