ds265188-port-t1-e1-j1-transc Maxim Integrated Products, Inc., ds265188-port-t1-e1-j1-transc Datasheet - Page 6

• Manufacturer Part Number: ds265188-port-t1-e1-j1-transc
• Description: Ds26518 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

DS26518 8-Port T1/E1/J1 Transceiver
Figure 11-15. T1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 282
Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit ................................................................. 282
Figure 11-17. E1 Receive-Side Timing.................................................................................................................... 283
Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 283
Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 284
Figure 11-20. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 284
Figure 11-21. E1 Receive-Side Interleave Bus Operation—BYTE Mode ............................................................... 285
Figure 11-22. E1 Receive-Side Interleave Bus Operation—FRAME Mode ............................................................ 286
Figure 11-23. E1 Receive-Side RCHCLKn Gapped Mode During Channel 1 ........................................................ 286
Figure 11-24. E1 Transmit-Side Timing................................................................................................................... 287
Figure 11-25. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 287
Figure 11-26. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 288
Figure 11-27. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 288
Figure 11-28. E1 Transmit-Side Interleave Bus Operation—BYTE Mode .............................................................. 289
Figure 11-29. E1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 290
Figure 11-30. E1 G.802 Timing ............................................................................................................................... 291
Figure 11-31. E1 Transmit-Side TCHCLKn Gapped Mode During Channel 1 ........................................................ 291
Figure 13-1. SPI Interface Timing Diagram ............................................................................................................. 295
Figure 13-2. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 297
Figure 13-3. Intel Bus Write Timing (BTS = 0)......................................................................................................... 297
Figure 13-4. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 298
Figure 13-5 Motorola Bus Write Timing (BTS = 1) .................................................................................................. 298
Figure 13-6. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 300
Figure 13-7. Receive-Side Timing—Elastic Store Enabled (T1 Mode) ................................................................... 300
Figure 13-8. Transmit Formatter Timing—Backplane ............................................................................................. 302
Figure 13-10. Transmit Formatter Timing—Elastic Store Enabled.......................................................................... 303
Figure 13-11. BPCLK1 Timing................................................................................................................................. 303
Figure 13-12. JTAG Interface Timing Diagram........................................................................................................ 304
Figure 14-1. JTAG Functional Block Diagram ......................................................................................................... 305
Figure 14-2. TAP Controller State Diagram............................................................................................................. 308
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