ds265188-port-t1-e1-j1-transc Maxim Integrated Products, Inc., ds265188-port-t1-e1-j1-transc Datasheet - Page 7

• Manufacturer Part Number: ds265188-port-t1-e1-j1-transc
• Description: Ds26518 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

DS26518 8-Port T1/E1/J1 Transceiver
LIST OF TABLES
Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14
Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15
Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16
Table 8-1. Detailed Pin Descriptions ......................................................................................................................... 20
Table 9-1. CLKO Frequency Selection ...................................................................................................................... 33
Table 9-2. Reset Functions........................................................................................................................................ 34
Table 9-3. Registers Related to the Elastic Store...................................................................................................... 37
Table 9-4. Elastic Store Delay After Initialization....................................................................................................... 38
Table 9-5. Registers Related to the IBO Multiplexer ................................................................................................. 40
Table 9-6. RSERn Output Pin Definitions (GTCR1.GIBO = 0).................................................................................. 44
Table 9-7. RSIGn Output Pin Definitions (GTCR1.GIBO = 0) ................................................................................... 44
Table 9-8. TSERn Input Pin Definitions (GTCR1.GIBO = 0) ..................................................................................... 45
Table 9-9. TSIGn Input Pin Definitions (GTCR1.GIBO = 0) ...................................................................................... 45
Table 9-10. RSYNCn Input Pin Definitions (GTCR1.GIBO = 0) ................................................................................ 46
Table 9-11. D4 Framing Mode................................................................................................................................... 49
Table 9-12. ESF Framing Mode ................................................................................................................................ 50
Table 9-13. SLC-96 Framing ..................................................................................................................................... 50
Table 9-14. E1 FAS/NFAS Framing .......................................................................................................................... 52
Table 9-15. Registers Related to Setting Up the Framer .......................................................................................... 53
Table 9-16. Registers Related to the Transmit Synchronizer.................................................................................... 54
Table 9-17. Registers Related to Signaling ............................................................................................................... 55
Table 9-18. Registers Related to SLC-96.................................................................................................................. 58
Table 9-19. Registers Related to T1 Transmit BOC.................................................................................................. 60
Table 9-20. Registers Related to T1 Receive BOC................................................................................................... 60
Table 9-21. Registers Related to T1 Transmit FDL................................................................................................... 61
Table 9-22. Registers Related to T1 Receive FDL.................................................................................................... 61
Table 9-23. Registers Related to E1 Data Link ......................................................................................................... 62
Table 9-24. Registers Related to Maintenance and Alarms...................................................................................... 64
Table 9-25. T1 Alarm Criteria .................................................................................................................................... 66
Table 9-26. Registers Related to Transmit RAI (Yellow Alarm) ................................................................................ 66
Table 9-27. Registers Related to Receive RAI (Yellow Alarm) ................................................................................. 67
Table 9-28. T1 Line Code Violation Counting Options .............................................................................................. 68
Table 9-29. E1 Line Code Violation Counting Options .............................................................................................. 68
Table 9-30. T1 Path Code Violation Counting Arrangements ................................................................................... 69
Table 9-31. T1 Frames Out of Sync Counting Arrangements ................................................................................... 69
Table 9-32. Registers Related to DS0 Monitoring ..................................................................................................... 70
Table 9-33. Registers Related to T1 In-Band Loop Code Generator ........................................................................ 72
Table 9-34. Registers Related to T1 In-Band Loop Code Detection ......................................................................... 73
Table 9-35. Register Related to Framer Payload Loopbacks ................................................................................... 74
Table 9-36. HDLC-64/HDLC-256 Controller Features............................................................................................... 75
Table 9-37. Registers Related to the HDLC-64......................................................................................................... 76
Table 9-38. Registers Related to the HDLC-256....................................................................................................... 81
Table 9-39. Recommended Supply Decoupling ........................................................................................................ 85
Table 9-40. Registers Related to Control of the LIU.................................................................................................. 88
Table 9-41. Telecommunications Specification Compliance for DS26518 Transmitters .......................................... 89
Table 9-42. Transformer Specifications..................................................................................................................... 89
Table 9-43. T1.231, G.775, and ETS 300 233 Loss Criteria Specifications.............................................................. 95
Table 9-44. Jitter Attenuator Standards Compliance................................................................................................. 97
Table 9-45. Registers Related to Configure, Control, and Status of BERT............................................................. 101
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