upd78f0124m6gba1-8et Renesas Electronics Corporation., upd78f0124m6gba1-8et Datasheet - Page 372

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upd78f0124m6gba1-8et

Manufacturer Part Number
upd78f0124m6gba1-8et
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode
and during the oscillation stabilization time.
clock is stopped, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time.
Monitoring is stopped when oscillation of the X1 input clock is stopped and during the oscillation stabilization time.
372
Internal oscillation clock
Internal oscillation clock
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the X1 input
Note The register that controls oscillation of the X1 input clock differs depending on the type of the clock supplied
(CLME = 1 is set when CPU clock operates on internal oscillation clock and before entering STOP mode)
Clock monitor status
Clock monitor status
to the CPU.
CPU operation
CPU operation
X1 input clock
X1 input clock
• When CPU operates on internal oscillation clock: Controlled by bit 7 (MSTOP) of the main OSC control
• When CPU operates on subsystem clock:
(CPU clock)
MSTOP or
MCC
(6) Clock monitor status after X1 input clock oscillation is stopped by software
CLME
CLME
Note
operation
Monitoring
Normal
Monitoring
(5) Clock monitor status after STOP mode is released
Figure 20-3. Timing of Clock Monitor (3/4)
Oscillation
Monitoring
Monitoring
Oscillation
stopped
stopped
stopped
stopped
Normal operation (internal oscillation clock or subsystem clock
STOP
CHAPTER 20 CLOCK MONITOR
User’s Manual U16315EJ3V1UD
Oscillation stabilization time
Oscillation stabilization time
(time set by OSTS register)
(time set by OSTS register)
Monitoring stopped
Clock supply
Monitoring stopped
17 clocks
stopped
register (MOC)
control register (PCC)
Controlled by bit 7 (MCC) of the processor clock
Normal operation
Monitoring
Note
)
Monitoring

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