upd78f0124m6gba1-8et Renesas Electronics Corporation., upd78f0124m6gba1-8et Datasheet - Page 542

• Manufacturer Part Number: upd78f0124m6gba1-8et
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

E.2 Revision History up to Previous Edition
each edition in which the revision was applied.
542
2nd edition
The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of
Edition
Addition of products
µ
Under development → Under mass production
µ
780124(A), 78F0124(A), 780121(A1), 780122(A1), 780123(A1), 780124(A1)
Modification of names of the following special function registers (SFRs)
• Ports 0 to 3, 6, 7, and 12 to 14 → Port registers 0 to 3, 6, 7, and 12 to 14
Addition of Cautions 3 and 4 to 1.4 Pin Configuration (Top View)
Modification of 1.5 K1 Family Lineup
Modification of outline of timer in and addition of Remark to 1.7 Outline of Functions
Addition of Table 2-1 Pin I/O Buffer Power Supplies
Modification of descriptions in 2.2.10 AV
versions only)
Modification of the following contents in Table 2-2 Pin I/O Circuit Types
• Modification of recommended connection when P60 to P63 are not used
• Modification of I/O circuit type of P62 and P63
• Addition of Note to AV
• Modification of recommended connection when V
Modification of Figure 3-14 Data to Be Saved to Stack Memory
Modification of Figure 3-15 Data to Be Restored from Stack Memory
Modification of [Description example] in 3.4.4 Short direct addressing
Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed addressing,
and 3.4.9 Stack addressing
Addition of Table 4-1 Pin I/O Buffer Power Supplies
Modification of Table 4-3 Port Configuration
Modification of Figure 4-10 Block Diagram of P20 to P27
Addition of Remark to Figure 4-16 Block Diagram of P130
Deletion of input switch control register (ISC) from and addition of port registers (P0 to P3, P6,
P7, P12 to P14) to 4.3 Registers Controlling Port Function
Partial modification of descriptions in 4.4.1 (1) Output mode, 4.4.3 (1) Output mode, and
(2) Input mode
Modification of Figure 5-1 Block Diagram of Clock Generator
Addition of Note to 5.3 (1) Processor clock control register (PCC)
Addition of Cautions 2 and 3 to Figure 5-6 Format of Oscillation Stabilization Time
Counter Status Register (OSTC)
Modification of Figure 5-8 Examples of External Circuit of X1 Oscillator, Figure 5-9
Examples of External Circuit of Subsystem Clock Oscillator, and Figure 5-10 Examples
of Incorrect Resonator Connection
Modification of Notes 4 and 5 in Figure 5-13 Status Transition Diagram (2)
Modification of Note 4 and illustration in Figure 5-13 Status Transition Diagram (4)
PD78F0124(A1), 780121(A2), 780122(A2), 780123(A2), 780124(A2)
PD780121, 780122, 780123, 780124, 78F0124, 780121(A), 780122(A), 780123(A),
REF
APPENDIX E REVISION HISTORY
User’s Manual U16315EJ3V1UD
REF
Description
, 2.2.13 REGC, and 2.2.18 V
PP
is not used
PP
(flash memory
Throughout
CHAPTER 1
OUTLINE
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4
PORT
FUNCTIONS
CHAPTER 5
CLOCK
GENERATOR
Applied to:
(1/4)