si4430 Silicon Laboratories, si4430 Datasheet - Page 109

• Manufacturer Part Number: si4430
• Description: Si4430 Ism Transceiver
• Manufacturer: Silicon Laboratories

Register 30h. Data Access Control
Reset value = 10001101
Name
Type
Bit
1:0
Bit
7
6
5
4
3
2
enpacrx
Reserved
crcdonly
enpacrx
enpactx
crc[1:0]
R/W
Name
lsbfrst
D7
encrc
Enable Packet RX Handling.
If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled.
Setting enpacrx = 1 will enable automatic packet handling in the RX path. Register
30–4D allow for various configurations of the packet structure. Setting enpacrx = 0 will
not do any packet handling in the RX path. It will only receive everything after the sync
word and fill up the RX FIFO.
LSB First Enable.
The LSB of the data will be transmitted/received first if this bit is set.
CRC Data Only Enable.
When this bit is set to 1 the CRC is calculated on and checked against the packet data
fields only.
Reserved.
Enable Packet TX Handling.
If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled.
Setting enpactx = 1 will enable automatic packet handling in the TX path. Register 30–4D
allow for various configurations of the packet structure. Setting enpactx = 0 will not do
any packet handling in the TX path. It will only transmit what is loaded to the FIFO.
CRC Enable.
Cyclic Redundancy Check generation is enabled if this bit is set.
CRC Polynomial Selection.
00:
01:
10:
11:
lsbfrst
R/W
D6
CCITT
CRC-16 (IBM)
IEC-16
Biacheva
crcdonly
R/W
D5
Preliminary Rev. 0.4
Reserved
R/W
D4
enpactx
Function
R/W
D3
encrc
R/W
D2
D1
crc[1:0]
Si4430
R/W
D0
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