si4430 Silicon Laboratories, si4430 Datasheet - Page 128

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si4430

Manufacturer Part Number
si4430
Description
Si4430 Ism Transceiver
Manufacturer
Silicon Laboratories
Datasheet

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Register 56h. Modem Test
Register 57h. Charge Pump Test
Si4430
Reset value = 00000000
Reset value = 00000000
128
Name
Name
Type
Type
Bit
Bit
2:0
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
cdcurr[2:0]
cpforceup
cpforcedn
bcrfbyp
oscdeten
fbdiv_rst
refclksel
refclkinv
pfdrst
cdconly
bcrfbyp
slicfbyp
distogg
R/W
R/W
Name
Name
dttype
D7
D7
pfdrst
ookth
fbdiv_rst
slicfbyp
If set, BCR phase compensation will be bypassed.
If set, slicer phase compensation will be bypassed.
Dithering Type.
If low and dither enabled, we add +1/0, otherwise if high and dithering enabled, we add
±1.
If low, the ADC Oscillation Detection mechanism is allowed to work. If set, we disable the
function.
If set, in OOK mode, the slicer threshold will be estimated by 8 bits of preamble. By
default, this bit is low and the demod estimate the threshold after 4 bits.
Delta-Sigma Reference Clock Source Selection
1:
0:
Delta-Sigma Reference Clock Inversion Enable.
If reset, the discriminator toggling is disabled.
Direct Control to Analog.
Direct Control to Analog.
Charge Pump Force Up.
Charge Pump Force Down.
Charge Pump DC Offset Only.
Charge Pump DC Current Selection.
R/W
R/W
D6
D6
10 MHz
PLL
cpforceup
dttype
R/W
R/W
D5
D5
Preliminary Rev. 0.4
cpforcedn
oscdeten
R/W
R/W
D4
D4
Function
Function
cdonly
ookth
R/W
R/W
D3
D3
refclksel
R/W
D2
D2
cdcurr[2:0]
refclkinv
R/W
R/W
D1
D1
distogg
R/W
D0
D0

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