si4430 Silicon Laboratories, si4430 Datasheet - Page 75

• Manufacturer Part Number: si4430
• Description: Si4430 Ism Transceiver
• Manufacturer: Silicon Laboratories

Add
0C
0D
1C
1D
2C
2D
3C
00
01
02
03
04
05
06
07
08
09
0A
0B
0E
0F
10
12
13
14
15
16
17
18
19
1A
1B
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W RSSI Threshold for Clear Channel Indicator
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
12. Reference Material
12.1. Complete Register Table and Descriptions
Clock Recovery Oversampling Ratio
Clock Recovery Timing Loop Gain 1
Clock Recovery Timing Loop Gain 0
Crystal Oscillator Load Capacitance
Clock Recovery Gearshift Override
Received Signal Strength Indicator
Low Battery Detector Threshold
Operating & Function Control 1
Operating & Function Control 2
Low-Duty Cycle Mode Duration
AFC Loop Gearshift Override
Antenna Diversity Register 1
Antenna Diversity Register 2
Microcontroller Output Clock
ADC Sensor Amplifier Offset
Temperature Sensor Control
Preamble Detection Control
Temperature Value Offset
Wake-Up Timer Period 1
Wake-Up Timer Period 2
Wake-Up Timer Period 3
Clock Recovery Offset 2
Clock Recovery Offset 1
Clock Recovery Offset 0
Wake-Up Timer Value 1
Wake-Up Timer Value 2
I/O Port Configuration
OOK Counter Value 1
OOK Counter Value 2
Battery Voltage Level
AFC Correction Read
GPIO0 Configuration
GPIO1 Configuration
GPIO2 Configuration
Data Access Control
AFC Timing Control
ADC Configuration
IF Filter Bandwidth
Transmit Header 3
Transmit Header 2
Transmit Header 1
Interrupt Enable 1
Interrupt Enable 2
Interrupt Status 1
Interrupt Status 2
Header Control 1
Header Control 2
Preamble Length
Slicer Peak Hold
Function/Desc
Device Version
EzMAC status
Device Status
Sync Word 3
Sync Word 2
Sync Word 1
Sync Word 0
Device Type
AFC Limiter
ADC Value
dwn3_bypass
adcstart/adc-
gpio0drv[1]
gpio1drv[1]
gpio2drv[1]
afc_corr[9]
afc_corr[9]
tsrange[1]
prealen[7]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
adrssi1[7]
adrssib[7]
Reserved
Reserved
ookcnt[7]
rxosr[10]
Afclim[7]
preath[4]
enswdet
antdiv[2]
ncoff[15]
crgain[7]
sync[31]
sync[23]
sync[15]
wtm[15]
rssith[7]
enpacrx
txhd[31]
txhd[23]
txhd[15]
tvoffs[7]
rxosr[7]
xtalshft
wtv[15]
ncoff[7]
sync[7]
wtm[7]
iswdet
enfferr
swres
adc[7]
wtv[7]
rssi[7]
ldc[7]
afcbd
done
ffovfl
ifferr
D7
Table 27. Register Descriptions
0
0
0
0
gpio0drv[0]
gpio1drv[0]
gpio2drv[0]
afc_corr[8]
afc_corr[9]
enpreaval
tsrange[0]
adrssia[6]
adrssib[6]
prealen[6]
entxffafull
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
adcsel[2]
ookcnt[6]
preath[3]
Preliminary Rev. 0.4
antdiv[1]
ncoff[14]
crgain[6]
Afclim[6]
attack[2]
extitst[2]
sync[30]
sync[22]
sync[14]
ipreaval
tvoffs[6]
wtm[14]
ndec[2]
rssith[6]
hdlen[2]
txhd[30]
txhd[22]
txhd[14]
itxffafull
rxready
rxosr[6]
rxosr[9]
ncoff[6]
wtv[14]
sync[6]
wtm[6]
adc[6]
rssi[6]
lsbfrst
rxcrc1
wtv[6]
enlbd
xlc[6]
ldc[6]
enafc
ffunfl
D6
0
0
0
bcen[3:0]
enpreainval
Reserved
afcgearh[2]
afc_corr[7]
entxffaem
adrssia[5]
adrssib[5]
prealen[5]
ipreainval
Reserved
Reserved
Reserved
Reserved
preath[2]
adcsel[1]
ookcnt[5]
ncoff[13]
crgain[5]
Afclim[5]
ookfrzen
antdiv[0]
extitst[1]
shwait[2]
attack[1]
crcdonly
sync[29]
sync[21]
sync[13]
itxffaem
entsoffs
tvoffs[5]
wtm[13]
ndec[1]
crfast[2]
rssith[5]
hdlen[1]
txhd[29]
txhd[21]
txhd[13]
rxosr[5]
rxosr[8]
ncoff[5]
wtv[13]
sync[5]
wtm[5]
pksrch
rxffem
adc[5]
clkt[1]
wtv[5]
rssi[5]
xlc[5]
ldc[5]
pup0
pup1
pup2
enwt
D5
0
0
0
afcgearh[1]
afc_corr[6]
peakdeten
prealen[4]
enrxffafull
Reserved
Reserved
adrssia[4]
adrssib[4]
Reserved
adcsel[0]
ookcnt[4]
ncoff[12]
crgain[4]
Afclim[4]
preath[1]
extitst[0]
shwait[1]
attack[0]
sync[28]
sync[20]
sync[12]
headerr
gpio0[4]
gpio1[4]
gpio2[4]
entstrim
tvoffs[4]
wtm[12]
ndec[0]
crfast[1]
rssith[4]
hdlen[0]
txhd[28]
txhd[20]
txhd[12]
irxffafull
x32ksel
rxosr[4]
ncoff[4]
wtv[12]
stallctrl
sync[4]
wtm[4]
vbat[4]
rxmpk
adc[4]
enrssi
clkt[0]
wtv[4]
lbdt[4]
rssi[4]
xlc[4]
wtr[4]
ldc[4]
vc[4]
dt[4]
pkrx
irssi
D4
Data
afcgearh[0]
afc_corr[5]
prealen[3]
adcoffs[3]
Reserved
adrssia[3]
adrssib[3]
ookcnt[3]
reserved
adcref[1]
madeten
preath[0]
ncoff[19]
ncoff[11]
crgain[3]
Afclim[3]
decay[3]
sync[27]
sync[19]
gpio0[3]
gpio1[3]
gpio2[3]
tstrim[3]
shwait[0]
crfast[0]
sync[11]
txhd[27]
txhd[19]
tvoffs[3]
wtm[11]
rssith[3]
enpactx
fixpklen
txhd[11]
rxosr[3]
ncoff[3]
sync[3]
wtv[11]
vbat[3]
pkvalid
wtm[3]
filset[3]
enwut
autotx
adc[3]
lbdt[3]
rssi[3]
enext
wtr[3]
wtv[3]
xlc[3]
ldc[3]
vc[3]
enlfc
itsdo
dt[3]
iwut
txon
iext
D3
afcgearl[2]
afc_corr[4]
ookcnt[10]
crgain[10]
synclen[1]
prealen[2]
rssi_off[2]
adcoffs[2]
adrssia[2]
adrssib[2]
enpksent
ookcnt[2]
reserved
adcref[0]
crslow[2]
ncoff[18]
ncoff[10]
crgain[2]
Afclim[2]
anwait[2]
decay[2]
crcerror
sync[26]
sync[18]
sync[10]
gpio0[2]
gpio1[2]
gpio2[2]
tstrim[2]
tvoffs[2]
wtm[10]
rssith[2]
txhd[26]
txhd[18]
txhd[10]
rxosr[2]
ncoff[2]
ipksent
mclk[2]
wtv[10]
sync[2]
wtm[2]
vbat[2]
filset[2]
enldm
adc[2]
wtv[2]
lbdt[2]
rssi[2]
enlbd
xlc[2]
wtr[2]
ldc[2]
encrc
vc[2]
dt[2]
rxon
dio2
ilbd
D2
hdch[3:0]
adcgain[1]
afcgearl[1]
afc_corr[3]
synclen[0]
prealen[1]
enchiprdy
adcoffs[1]
adrssia[1]
adrssib[1]
rssi_off[1]
enpkvalid
ookcnt[1]
crslow[1]
ookcnt[9]
ncoff[17]
crgain[9]
crgain[1]
Afclim[1]
decay[1]
sync[25]
sync[17]
gpio0[1]
gpio1[1]
gpio2[1]
tstrim[1]
anwait[1]
txhd[25]
txhd[17]
ipkvalid
ichiprdy
tvoffs[1]
rxosr[1]
rssith[1]
mclk[1]
ncoff[9]
ncoff[1]
sync[9]
sync[1]
vbat[1]
txhd[9]
wtm[9]
wtm[1]
filset[1]
cps[1]
adc[1]
wtv[9]
wtv[1]
lbdt[1]
rssi[1]
ffclrrx
wtr[1]
crc[1]
xlc[1]
ldc[1]
vc[1]
pllon
dt[1]
pktx
dio1
Si4430
D1
afcgearl[0]
afc_corr[2]
encrcerror
adcgain[0]
adcoffs[0]
adrssia[0]
adrssib[0]
prealen[8]
prealen[0]
rssi_off[0]
crslow[0]
ookcnt[8]
ookcnt[0]
ncoff[16]
crgain[8]
crgain[0]
Afclim[0]
decay[0]
icrcerror
gpio0[0]
gpio1[0]
gpio2[0]
tstrim[0]
anwait[0]
sync[24]
sync[16]
txhd[24]
txhd[16]
tvoffs[0]
rssith[0]
rxosr[0]
ncoff[8]
ncoff[0]
mclk[0]
sync[8]
sync[0]
wtm[8]
wtm[0]
vbat[0]
filset[0]
pksent
txhd[8]
adc[0]
lbdt[0]
rssi[0]
cps[0]
enpor
wtv[8]
wtv[0]
ffclrtx
xlc[0]
wtr[0]
ldc[0]
crc[0]
vc[0]
dt[0]
xton
dio0
ipor
D0
75
Default
00111
POR
BCh
7Fh
0Ah
AEh
8Fh
1Eh
1Dh
0Ch
2Ah
2Dh
D4h
04h
00h
03h
01h
00h
06h
00h
00h
00h
00h
00h
00h
20h
00h
03h
00h
01h
00h
14h
01h
40h
03h
64h
01h
47h
02h
00h
00h
18h
26h
22h
08h
00h
00h
00h
00h
00h
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