si4430 Silicon Laboratories, si4430 Datasheet - Page 123

• Manufacturer Part Number: si4430
• Description: Si4430 Ism Transceiver
• Manufacturer: Silicon Laboratories

dtb[4:0]
Register 51h. Digital Test Bus Select
Reset value = 00000000
Name
Type
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
11
0
1
2
3
4
5
6
7
8
9
Bit
5:0
Bit
7
6
vco_cal_rst_s_n
pll_lock_detect
wkup_clk_32k
wkup_clk_32k
tsadc_needed
gpio_0_oen_n
start_full_sync
dsm_clk_mux
trdata_on_sdi
en_div_sync
sdo_aux_sel
bandgap_en
ch_freq_req
vco_cal_en
vco_cal_en
vco_cal_en
coarse_rdy
ts_adc_en
pll_pfd_up
osc30_en
div_clk_g
cont_lbd
int_ack1
ext_int2
Reserved
pwst[0]
GPIO0
dsm[0]
dsm[3]
pll_en
pll_en
Reserved
xok
ensctest
dtb[5:0]
R/W
Name
D7
Table 33. Internal Digital Signals Available on the Digital Test Bus
clock divider enable (sync'ed)
low battery continuous mode
RC osc. full calibration start
RC osc. coarse cal. ready
frequency change request
ext. interrupt from GPIO2
SDO aux. function select
PLL enable: TUNE state
PLL enable: TUNE state
interrupt acknowledge 1
VCO calibration enable
VCO calibration enable
VCO calibration enable
DSM multiplexed clock
wake-up 32kHz clock
wake-up 32kHz clock
VCO calibration reset
GPIO0 output enable
internal power state
gated divided clock
TX/RX data on SDI
delta-sigma output
delta-sigma output
ensctest
aux. ADC enable
aux. ADC enable
Reserved.
Scan Test Enable.
When set to 1 then GPIO0 will be the ScanEn input.
Digital Test Bus.
GPIO must be configured to Digital Test Mux output.
oscillator enable
bandgap enable
PLL lock detect
PFD up signal
R/W
D6
chip ready
Signal
D5
pll_vbias_shunt_en
start_fine_sync
pll_lock_detect
osc30_bias2x
pll_fb_clk_tst
pll_pfd_down
gpio_0_aen
frac_div_en
adc_rdy_n
en_ref_cnt
pll_fbdiv15
ext_retran
rbase_en
zero_cap
wake_up
en_ckout
sdo_aux
int_ack2
fine_rdy
vco_cal
pos_diff
pllt0_ok
irq_bit8
tx_mod
pllts_ok
GPIO1
pwst[1]
lbd_on
dsm[1]
uc_clk
pll_en
Preliminary Rev. 0.4
D4
RC osc. fine calibration start
aux. ADC conversion ready
ext. retransmission request
VCO calibration is running
positive difference to goal
combined external status
reference counter enable
PLL enable: TUNE state
GPIO0 analog selection
interrupt acknowledge 2
fractional divider enable
VCO bias shunt enable
RC osc. fine cal. ready
low battery ON signal
PLL initial settling OK
oscillator bias control
microcontroller clock
TX modulation input
PLL soft settling OK
PLL feedback clock
internal power state
delta-sigma output
first divided clock
PFD down signal
clock out enable
SDO aux. signal
PLL lock detect
wake-up event
cap. load zero
Function
Signal
D3
dtb[5:0]
R/W
D2
osc30_buff_en
en_freq_cnt_s
en_freq_cnt_s
xtal_req_sync
vco_cal_done
vco_cal_done
pll_ref_clk_tst
pfd_up_down
gpio_0_aden
tx_mod_gpio
nirq_aux_sel
dsm_rst_s_n
ckout_rcsel
en_ckout_s
tx_clk_out
adc_done
clk_base
msk_bit8
prog_req
int_store
buff3_en
xtal_req
pllt0_ok
tm1sec
pllts_ok
pllts_ok
GPIO2
pwst[2]
dsm[2]
xok
lbd
D1
aux. ADC measurement done
GPIO0 ADC input line enable
PFD output change (XOR'ed)
frequency recalculation req.
crystal req. for RC osc. cal.
combined masked ext. int.
clock out enable (sync'ed)
frequency counter enable
frequency counter enable
nIRQ aux. function select
unfiltered output of LBD
sync'ed crystal request
VCO calibration done
VCO calibration done
PLL initial settling OK
interrupt latch closed
TX modulation input
PLL reference clock
PLL soft settling OK
PLL soft settling OK
internal power state
slow clock selected
delta-sigma output
delta-sigma reset
Si4430
1 sec timebase
TX clock output
timebase clock
buffer3 enable
buffer enable
chip ready
Signal
D0
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