si4430 Silicon Laboratories, si4430 Datasheet - Page 124

• Manufacturer Part Number: si4430
• Description: Si4430 Ism Transceiver
• Manufacturer: Silicon Laboratories

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demod phase[4]
agc_smp_clk
agc_smp_clk
ch_freq_req
pk_sent_dly
direct_mode
ramp_done
retran_req
pa_on_trig
pa_on_trig
reg_wr_en
prea_valid
prea_valid
data_start
data_start
tx_shdwn
dp_tx_en
dp_rx_en
prog_req
clk_mod
mod_en
mod_en
sync_ok
sync_ok
pk_srch
adc_en
GPIO0
bit_clk
ldc_on
ldc_on
tx_ffaf
tx_en
pk_rx
Table 33. Internal Digital Signals Available on the Digital Test Bus (Continued)
ts_en
xok
modulator gated 10MHz clock
sync. word has been detected
sync. word has been detected
freq. channel update request
packet handler (RX) enable
temperature sensor enable
packet handler (TX) enable
frequency change request
chip ready: READY state
packet is being searched
demodulator phase MSB
packet is being received
data input start from PH
retransmission request
active low duty cycle
active low duty cycle
delayed packet sent
register write enable
TX enable: TX state
TX enable: TX state
TX FIFO almost full
AGC sample clock
AGC sample clock
modulator enable
modulator enable
start of TX data
valid preamble
valid preamble
PA ON trigger
TX shutdown
ramp is done
ADC enable
direct mode
bit clock
Signal
ldo_rf_precharge
demod phase [3]
tx_shdwn_done
adc_refdac_en
tx_fifo_wr_en
demod_tst[2]
win_h_dly_tp
no_sync_det
tx_ffpt_store
dly_5us_ok
auto_tx_on
ramp_start
ramp_start
reg_rd_en
prea_valid
prea_valid
prea_inval
data_start
data_start
dp_tx_en
crc_error
win_h_tp
return_tx
sync_ok
sync_ok
freq_err
ook_en
GPIO1
tx_out
tx_rdy
rx_ffaf
bit_clk
pll_en
tx_clk
pll_en
Preliminary Rev. 0.4
start modulator ramping down
sync. word has been detected
sync. word has been detected
CRC error has been detected
ADC reference DAC enable
packet handler (TX) enable
modulator ramp down start
packet handler TX data out
PLL enable: TUNE state
window comparator high
window comparator high
PLL enable: TUNE state
OOK modulation enable
no sync word detected
TX FIFO pointer store
TX FIFO write enable
wrong freq. indication
register rdead enable
demodulator MSB-1
TX clock from NCO
RX FIFO almost full
RF LDO precharge
TX shutdown done
5 us delay expired
automatic TX ON
demodulator test
invalid preamble
start of TX data
start of TX data
return from TX
valid preamble
valid preamble
TX ready
bit clock
Signal
ook (also internal
demod phase [2]
tx_ffpt_restore
dsm_rst_s_n
rx_fifo_rd_en
demod_tst[1]
pa_ramp_en
pa_ramp_en
mod_dly_ok
win_l_dly_tp
ramp_done
ramp_done
tx_ffem_tst
ant_div_sw
hdch_error
prea_valid
rd_clk_x8
adc_rst_n
addr_inc
mod_en
pk_valid
win_l_tp
pk_sent
pk_sent
pk_sent
pk_srch
rx_data
rx_data
rx_data
GPIO2
tx_clk
tx_en
tx_off
pk_tx
rx_en
PN9)
packet handler RX data input
modulator ramp down ended
window comparator low dly’d
window comparator low dly’d
demodulator RX data output
demodulator RX data output
antenna switch (algorythm)
register address increment
packet is being transmitted
packet is being searched
modulator delay expired
TX FIFO pointer restore
internal TX FIFO empty
read clock = tx_clk / 10
header error detected
packet has been sent
packet has been sent
modulator ramp done
RX FIFO read enable
valid packet received
combined ADC reset
demodulator MSB-2
RX enable: RX state
TX enable: TX state
TX clock from NCO
modulator enable
demodulator test
OOK modulation
PA ramp enable
PA ramp enable
dsm sync. reset
valid preamble
packet sent
TX OFF
Signal