nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 22

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

9 0 Timing and Control
A reset to the CPU will force both IFF
state disabling maskable interrupts They can be enabled by
an EI instruction at any time by the programmer When an EI
instruction is executed any pending interrupt requests will
not be accepted until after the instruction following EI has
been executed This single instruction delay is necessary in
situations where the following instruction is a return instruc-
tion and interrupts must not be allowed until the return has
been completed The EI instruction sets both IFF
1
(Continued)
and IFF
2
to the reset
FIGURE 17 Interrupt Mode 2
1
and IFF
2
22
to the enable state When the CPU accepts an interrupt
both IFF
interrupts until the programmer wishes to issue a new EI
instruction Note that for all the previous cases IFF
IFF
The function of IFF
non-maskable interrupt occurs When a non-maskable inter-
rupt is accepted IFF
until reenabled by the programmer Thus after a non-mask-
able interrupt has been accepted maskable interrupts are
disabled but the previous state of IFF
2
are always equal
1
and IFF
2
are automatically reset inhibiting further
2
1
is to retain the status of IFF
is reset to prevent further interrupts
TL C 5171– 27
1
is saved by IFF
1
when a
1
and
2