nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 56

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

12 14 Program Control
DJNZ
Decrement the B register and conditionally jump to program
location calculated with respect to the program counter and
the displacement d based on the contents of the B register
B
If B
else PC
Timing
Addressing Mode
CALLS
CALL
Unconditional call to subroutine at location nn
(SP
(SP
SP
PC
Timing
Addressing Mode
CALL
Conditional call to subroutine at location nn based on test-
able flag stages
If cc true
(SP
(SP
SP
PC
else continue
Timing
Addressing Mode
7
0
7
1
7
1
e
b
b
b
b
6
1
6
0
6
1
n (high-order byte)
n (high-order byte)
n (low-order byte)
n (low-order byte)
0 continue
B
1)
2)
1)
2)
SP
SP
5
5
0
nn
5
0
nn
b
d
nn
cc nn
1
d
If B
If B
b
b
cc
If cc true
If cc not true
4
1
4
0
4
PC
b
PC
PC
PC
PC
2
2
i
e
3
0
3
1
2
3
a
H
L
H
L
0
0
d
2
0
2
1
2
1
1
0
1
0
1
0
0
0
0
1
0
0
No flags affected
M cycles
T states
M cycles
T states
PC Relative
No flags affected
M Cycles
T states
Direct
No flags affected
M cycles
T states 17 (4 3 4 3 3)
M cycles
T states
Direct
(Continued)
13 (5 3 5)
8 (5 3)
17 (4 3 4 3 3)
10 (4 3 3)
3
2
5
3
5
56
RETURNS
RET
Unconditional return from subroutine or other return to pro-
gram location pointed to by the top of the stack
PC
PC
SP
Timing
Addressing Mode
RET
Conditional return from subroutine or other return to pro-
gram location pointed to by the top of the stack
If cc true
PC
PC
SP
else continue
Timing
Addressing Mode
RETI
Unconditional return from interrupt handling subroutine
Functionally identical to RET instruction Unique opcode al-
lows monitoring by external hardware
PC
PC
SP
Timing
Addressing Mode
7
1
7
1
7
1
0
L
H
L
H
L
H
6
1
6
1
6
1
1
SP
SP
SP
5
0
5
5
1
0
cc
(SP)
(SP)
(SP)
(SP
(SP
(SP
cc
If cc true
If cc not true
a
a
a
4
0
4
4
0
0
a
a
a
2
2
2
3
1
3
3
1
1
1)
1)
1)
2
0
2
0
2
1
1
1
0
1
0
1
0
0
0
1
0
0
0
1
1
No flags affected
M cycles
T states
Register Indirect
No flags affected
M cycles
T states
M cycles
T states
Register Indirect
No flags affected
M cycles
T states
Register Indirect
10 (4 3 3)
11 (5 3 3)
5
14 (4 4 3 3)
3
3
1
4