nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 29

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

12 1 Instruction Set Index
DI
DJNZ d
EI
EX (SP) ss
EX AF A’F’
EX DE HL
EXX
HALT
IM 0
IM 1
IM 2
IN A (n)
IN r (C)
INC m
INC r
INC rr
IND
INDR
INI
INIR
JP cc nn
JP nn
JP (ss)
JR d
JR kk d
LD A I
LD A m
LD A R
LD I A
LD m
LD m
LD m
LD (nn) rr
LD r m
LD r n
LD R A
LD r
LD rr (nn)
LD rr nn
LD SP ss
LDD
LDDR
LDI
LDIR
NEG
NOP
Alphabetical
Mnemonic
d
Assembly
1
1
2
r
1
1
s
n
r
A
2
Disable interrupts
Decrement B and jump relative B
Enable interrupts
Exchange the location (SP) with register ss
Exchange the contents of AF and A’F’
Exchange the contents of DE and HL
Exchange the contents of BC DE and HL with the contents
Halt (wait for interrupt or reset)
Set interrupt mode 0
Set interrupt mode 1
Set interrupt mode 2
Load Accumulator with input from device (n)
Load register r with input from device (C)
Increment data in memory location m
Increment register r
Increment contents of register pair rr
Load location (HL) with input from port (C) decrement HL and B
Load location (HL) with input from port (C) decrement HL and B repeat until B
Load location (HL) with input from port (C) increment HL decrement B
Load location (HL) with input from port (C) increment HL decrement B
Jump to location nn if condition cc is true
Unconditional jump to location nn
Unconditional jump to location (ss)
Unconditional jump relative to PC
Jump relative to PC
Load Accumulator with register I contents
Load Accumulator from location m
Load Accumulator with register R contents
Load register I with Accumulator contents
Load memory with immediate data n
Load memory from register r
Load memory from Accumulator
Load memory location nn with register pair rr
Load register r from memory
Load register with immediate data n
Load register R from Accumulator
Load destination register r
Load register pair rr from memory location nn
Load register pair rr with immediate data nn
Load SP from register pair ss
Load location (DE) with location (HL) decrement DE HL and BC
Load location (DE) with location (HL) decrement DE HL and BC repeat until BC
Load location (DE) with location (HL) increment DE and HL decrement BC
Load location (DE) with location (HL) increment DE and HL decrement BC
Negate Accumulator (2’s complement)
No operation
repeat until B
repeat until BC
of B’C D’E’ and H’L’ respectively
e
e
(Continued)
0
a
0
d if kk true
d
from source register r
i
a
2
0
d
1
29
Operation
s
e
e
0
0
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